-
公开(公告)号：US20220231034A1
公开(公告)日：2022-07-21
申请号：US17712495
申请日：2022-04-04
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tzu-Yu Chen , Kuo-Chi Tu , Fu-Chen Chang , Chih-Hsiang Chang , Sheng-Hung Shih
IPC: H01L27/11507 , H01L27/11504 , G11C11/22 , H01L49/02
Abstract: In an embodiment, a structure includes one or more first transistors in a first region of a device, the one or more first transistors supporting a memory access function of the device. The structure includes one or more ferroelectric random access memory (FeRAM) capacitors in a first inter-metal dielectric (IMD) layer over the one or more first transistors in the first region. The structure also includes one or more metal-ferroelectric insulator-metal (MFM) decoupling capacitors in the first IMD layer in a second region of the device. The MFM capacitors may include two or more capacitors coupled in series to act as a voltage divider.
-
公开(公告)号：US11257844B2
公开(公告)日：2022-02-22
申请号：US16569487
申请日：2019-09-12
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Tzu-Yu Chen , Sheng-Hung Shih , Kuo-Chi Tu , Wen-Ting Chu
IPC: H01L27/1159 , H01L23/522
Abstract: A semiconductor device includes a lower intermetal dielectric (IMD) layer, a middle conductive line, and a ferroelectric random access memory (FRAM) structure. The middle conductive line is embedded in the lower IMD layer. The FRAM structure is over the lower IMD layer and the middle conductive line. The FRAM structure includes a bottom electrode, a ferroelectric layer, and a top electrode. The bottom electrode is over the middle conductive line and in contact with the lower IMD layer. The ferroelectric layer is over the bottom electrode. The top electrode is over the ferroelectric layer.
-
公开(公告)号：US20210343731A1
公开(公告)日：2021-11-04
申请号：US17376531
申请日：2021-07-15
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tzu-Yu Chen , Kuo-Chi Tu , Sheng-Hung Shih , Fu-Chen Chang
IPC: H01L27/11507 , H01L49/02
Abstract: Some embodiments relate to a ferroelectric random access memory (FeRAM) device. The FeRAM device includes a bottom electrode structure and a top electrode overlying the ferroelectric structure. The top electrode has a first width as measured between outermost sidewalls of the top electrode. A ferroelectric structure separates the bottom electrode structure from the top electrode. The ferroelectric structure has a second width as measured between outermost sidewalls of the ferroelectric structure. The second width is greater than the first width such that the ferroelectric structure includes a ledge that reflects a difference between the first width and the second width. A dielectric sidewall spacer structure is disposed on the ledge and covers the outermost sidewalls of the top electrode.
-
公开(公告)号：US11004975B2
公开(公告)日：2021-05-11
申请号：US16940335
申请日：2020-07-27
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Kuo-Chi Tu , Jen-Sheng Yang , Sheng-Hung Shih , Tong-Chern Ong , Wen-Ting Chu
IPC: H01L29/78 , H01L29/51 , G11C11/22 , H01L27/1159 , H01L27/11592 , H01L29/66
Abstract: A semiconductor device includes a memory circuit and a logic circuit. The memory circuit includes a word line, a bit line, a common line and a memory transistor having a gate coupled to the word line, a drain coupled to the bit line and a source coupled to the common line. The logic circuit includes a field effect transistor (FET) having a gate, a drain and a source. The memory transistor has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a first insulating layer and a first ferroelectric (FE) material layer. The FET has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a second insulating layer and a second FE material layer.
-
公开(公告)号：US20210035992A1
公开(公告)日：2021-02-04
申请号：US16663952
申请日：2019-10-25
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tzu-Yu Chen , Kuo-Chi Tu , Sheng-Hung Shih , Wen-Ting Chu , Chih-Hsiang Chang , Fu-Chen Chang
IPC: H01L27/11502
Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a plurality of lower interconnect layers disposed within a lower dielectric structure over a substrate. A lower insulating structure is over the lower dielectric structure and has sidewalls extending through the lower insulating structure. A bottom electrode is arranged along the sidewalls and an upper surface of the lower insulating structure. The upper surface of the lower insulating structure extends past outermost sidewalls of the bottom electrode. A data storage structure is disposed on the bottom electrode and is configured to store a data state. A top electrode is disposed on the data storage structure. The bottom electrode has interior sidewalls coupled to a horizontally extending surface to define a recess within an upper surface of the bottom electrode. The horizontally extending surface is below the upper surface of the lower insulating structure.
-
公开(公告)号：US10796759B2
公开(公告)日：2020-10-06
申请号：US16413937
申请日：2019-05-16
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chin-Chieh Yang , Chih-Yang Chang , Chang-Sheng Liao , Hsia-Wei Chen , Jen-Sheng Yang , Kuo-Chi Tu , Sheng-Hung Shih , Wen-Ting Chu , Manish Kumar Singh , Chi-Tsai Chen
Abstract: The present disclosure, in some embodiments, relates to a method of operating a resistive random access memory (RRAM) array. The method includes applying a word-line voltage to a selected word-line during a read operation. A non-zero voltage is applied to a selected bit-line during the read operation. A first voltage is applied to a selected source-line during the read operation. The first voltage is smaller than a second voltage applied to an unselected source-line during the read operation.
-
公开(公告)号：US20190386204A1
公开(公告)日：2019-12-19
申请号：US16552169
申请日：2019-08-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hsia-Wei Chen , Chih-Yang Chang , Chin-Chieh Yang , Jen-Sheng Yang , Sheng-Hung Shih , Tung-Sheng Hsiao , Wen-Ting Chu , Yu-Wen Liao , I-Ching Chen
IPC: H01L43/02 , H01L23/538 , H01L43/12
Abstract: Various embodiments of the present application are directed towards a method for forming a flat via top surface for memory, as well as an integrated circuit (IC) resulting from the method. In some embodiments, an etch is performed into a dielectric layer to form an opening. A liner layer is formed covering the dielectric layer and lining the opening. A lower body layer is formed covering the dielectric layer and filling a remainder of the opening over the liner layer. A top surface of the lower body layer and a top surface of the liner layer are recessed to below a top surface of the dielectric layer to partially clear the opening. A homogeneous upper body layer is formed covering the dielectric layer and partially filling the opening. A planarization is performed into the homogeneous upper body layer until the dielectric layer is reached.
-
公开(公告)号：US20190123271A1
公开(公告)日：2019-04-25
申请号：US16227096
申请日：2018-12-20
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chih-Yang Chang , Wen-Ting Chu , Kuo-Chi Tu , Yu-Wen Liao , Hsia-Wei Chen , Chin-Chieh Yang , Sheng-Hung Shih , Wen-Chun You
Abstract: The present disclosure, in some embodiments, relates to a memory device. The memory device includes a bottom electrode via and a bottom electrode over a top of the bottom electrode via. A data storage layer is over the bottom electrode and a top electrode is over the data storage layer. A top electrode via is on an upper surface of the top electrode and is centered along a first line that is laterally offset from a second line centered upon a bottommost surface of the bottom electrode via. The first line is perpendicular to the upper surface of the top electrode and parallel to the second line.
-
公开(公告)号：US10199575B2
公开(公告)日：2019-02-05
申请号：US15223399
申请日：2016-07-29
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chih-Yang Chang , Wen-Ting Chu , Kuo-Chi Tu , Yu-Wen Liao , Hsia-Wei Chen , Chin-Chieh Yang , Sheng-Hung Shih , Wen-Chun You
Abstract: The present disclosure relates to a resistive random access memory (RRAM) device. The RRAM device has a bottom electrode arranged over a bottom electrode via. A variable resistive dielectric layer is arranged over the bottom electrode. The variable resistive dielectric layer extends to within a recess in an upper surface of the bottom electrode. A top electrode is disposed over the variable resistive dielectric layer. A top electrode via extends outward from an upper surface of the top electrode at a position centered along a first axis that is laterally offset from a second axis centered upon the recess within the upper surface of the bottom electrode. The top electrode via has a smaller total width than the top electrode.
-
公开(公告)号：US20180019390A1
公开(公告)日：2018-01-18
申请号：US15715413
申请日：2017-09-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hsia-Wei Chen , Wen-Ting Chu , Kuo-Chi Tu , Chih-Yang Chang , Chin-Chieh Yang , Yu-Wen Liao , Wen-Chun You , Sheng-Hung Shih
CPC classification number: H01L45/1233 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/08 , H01L45/085 , H01L45/12 , H01L45/122 , H01L45/124 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/16 , H01L45/1666 , H01L45/1683
Abstract: Some embodiments relate to an integrated circuit device, which includes a bottom electrode, a dielectric layer, and top electrode. The dielectric layer is disposed over the bottom electrode. The top electrode is disposed over the dielectric layer, and an upper surface of the top electrode exhibits a recess. A via is disposed over the top electrode. The via makes electrical contact with only a tapered sidewall of the recess without contacting a bottom surface of the recess.
