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1.发明申请公开(公告)号：US20250098558A1
公开(公告)日：2025-03-20
申请号：US18828335
申请日：2024-09-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hajun SUNG , Minwoo CHOI , Youngjae KANG , Kiyeon YANG , Changseung LEE
Abstract: A chalcogenide-based memory material may include a ternary semiconductor compound having a composition represented by XaY′bSec, wherein the chalcogenide-based memory material may have an ovonic threshold-switching (OTS) characteristic, and a threshold voltage of the chalcogenide-based memory material may change according to a polarity and an intensity of an applied voltage. In XaY′bSec, X≠Y, a+b+c=1, a>0.12, b>0.18, c≥0.4, and X and Y′ independently may be different ones of In, Sb, Ga, Sn, Al, Ge, Si, and P. A memory device may include the chalcogenide-based memory material. An electronic apparatus may include the memory device.
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公开(公告)号：US20240324246A1
公开(公告)日：2024-09-26
申请号：US18594355
申请日：2024-03-04
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kiyeon YANG , Donggeon GU , Bonwon KOO , Jeonghee PARK , Hajun SUNG , Dongho AHN , Zhe WU , Changseung LEE , Minwoo CHOI
CPC classification number: H10B63/24 , H10B63/84 , H10N70/841 , H10N70/8825 , H10N70/8828
Abstract: Provided are a self-selecting memory device having polarity dependent threshold voltage shift characteristics and/or a memory apparatus including the self-selecting memory device. The memory device includes a first electrode, a second electrode apart from and facing the first electrode, and a memory layer between the first electrode and the second electrode. The memory layer has Ovonic threshold switching characteristics and is configured to have a threshold voltage of the memory layer be changed as a density of active traps in the memory layer is changed, the threshold voltage changing according to the polarity and the intensity of a bias voltage applied to the memory layer. Furthermore, an element composition distribution is configured to be maintained constant in the memory layer in response to the threshold voltage of the memory layer changing.
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3.发明公开公开(公告)号：US20240032308A1
公开(公告)日：2024-01-25
申请号：US18478776
申请日：2023-09-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Wooyoung YANG , Bonwon KOO , Chungman KIM , Kwangmin PARK , Hajun SUNG , Dongho AHN , Changseung LEE , Minwoo CHOI
CPC classification number: H10B63/24 , G11C13/0004 , H10B61/10 , H10B63/84 , H10N50/01 , H10N50/80 , H10N70/24 , H10N70/25 , H10N70/063 , H10N70/231 , H10N70/8413 , H10N70/8825 , H10N70/8828 , H10N70/8833 , H10N70/8836
Abstract: A chalcogen compound layer exhibiting ovonic threshold switching characteristics, a switching device, a semiconductor device, and/or a semiconductor apparatus including the same are provided. The switching device and/or the semiconductor device may include two or more chalcogen compound layers having different energy band gaps. Alternatively, the switching device and/or semiconductor device may include a chalcogen compound layer having a concentration gradient of an element of boron (B), aluminum (Al), scandium (Sc), manganese (Mn), strontium (Sr), and/or indium (In) in a thickness direction thereof. The switching device and/or a semiconductor device may exhibit stable switching characteristics while having a low off-current value (leakage current value).
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公开(公告)号：US20230088249A1
公开(公告)日：2023-03-23
申请号：US17717611
申请日：2022-04-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Wooyoung YANG , Segab KWON , Hajun SUNG , Dongho AHN , Changseung LEE , Minwoo CHOI
Abstract: Provided are a semiconductor device and a semiconductor apparatus. The semiconductor device may include a first electrode; a second electrode spaced apart from the first electrode; and a selection device layer including a chalcogen compound layer between the first electrode and the second electrode and a metal oxide doped in the chalcogen compound layer. In the semiconductor device, by doping the metal oxide, an off-current value (leakage current value) of the selection device layer may be reduced, and static switching characteristics may be implemented.
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公开(公告)号：US20230042262A1
公开(公告)日：2023-02-09
申请号：US17522197
申请日：2021-11-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Minwoo CHOI , Bonwon KOO , Yongyoung PARK , Hajun SUNG , Dongho AHN , Kiyeon YANG , Wooyoung YANG , Changseung LEE
Abstract: Provided are a switching device and a memory device including the switching device. The switching device includes first and second electrodes, and a switching material layer provided between the first and second electrodes and including a chalcogenide. The switching material layer includes a core portion and a shell portion covering a side surface of the core portion. The switching layer includes a material having an electrical resistance greater than an electrical resistance of the core portion, for example in at least one of the core portion or the shell portion.
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Patent Agency Ranking
公开(公告)号：US20220406842A1
公开(公告)日：2022-12-22
申请号：US17523363
申请日：2021-11-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hajun SUNG , Bonwon KOO , Segab KWON , Yongyoung PARK , Dongho AHN , Kiyeon YANG , Wooyoung YANG , Changseung LEE , Minwoo CHOI
Abstract: Provided are a chalcogenide material, and a device and a memory device each including the same. The chalcogenide material may include: germanium (Ge) as a first component; arsenic (As) as a second component; at least one element selected from selenium (Se) and tellurium (Te) as a third component; and at least one element selected from the elements of Groups 2, 16, and 17 of the periodic table as a fourth component, wherein a content of the first component may be from 5 at % to 30 at %, a content of the second component may be from 20 at % to 40 at %, a content of the third component may be from 25 at % to 75 at %, and a content of the fourth component may be from 0.5 at % to 5 at %.
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7.发明申请公开(公告)号：US20220140003A1
公开(公告)日：2022-05-05
申请号：US17244212
申请日：2021-04-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Wooyoung YANG , Bonwon KOO , Chungman KIM , Kwangmin PARK , Hajun SUNG , Dongho AHN , Changseung LEE , Minwoo CHOI
Abstract: A chalcogen compound layer exhibiting ovonic threshold switching characteristics, a switching device, a semiconductor device, and/or a semiconductor apparatus including the same are provided. The switching device and/or the semiconductor device may include two or more chalcogen compound layers having different energy band gaps. Alternatively, the switching device and/or semiconductor device may include a chalcogen compound layer having a concentration gradient of an element of boron (B), aluminum (Al), scandium (Sc), manganese (Mn), strontium (Sr), and/or indium (In) in a thickness direction thereof. The switching device and/or a semiconductor device may exhibit stable switching characteristics while having a low off-current value (leakage current value).
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公开(公告)号：US20250133970A1
公开(公告)日：2025-04-24
申请号：US18444206
申请日：2024-02-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Minwoo CHOI , Hajun SUNG , Bonwon KOO , Kiyeon YANG , Changseung LEE
Abstract: Provided are a chalcogenide-based memory device capable of implementing multi-level memory and an electronic apparatus including the chalcogenide-based memory device. The memory device includes a first electrode and a second electrode arranged to be spaced apart from each other, and a memory layer provided between the first electrode and the second electrode and including a plurality of memory material layers having different threshold voltages from each other. Each of the plurality of memory material layers includes a chalcogenide-based material, has an ovonic threshold switching (OTS) characteristic, and is configured to have a threshold voltage varying depending on a polarity and intensity of an applied voltage.
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公开(公告)号：US20250149084A1
公开(公告)日：2025-05-08
申请号：US18785752
申请日：2024-07-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Changseung LEE , Minwoo CHOI , Bonwon KOO , Hajun SUNG , Kiyeon YANG
Abstract: Provided are a memory device for implementing a multi-level memory and a method of implementing a multi-level memory by using the memory device. The memory device includes first and second electrodes apart from each other, a self-selecting memory layer between the first and second electrodes having an ovonic threshold switching characteristic, including a chalcogenide-based material, and configured to have a threshold voltage varying depending on a polarity of and strength of a voltage applied thereto, and a resistive memory layer between the second electrode and the self-selecting memory layer and having a resistance characteristic varying depending on a voltage applied thereto. The memory device is configured to implement multi-level resistance states by changing at least one of a pulse polarity, a number of pulses, pulse height, and a pulse width of a voltage applied between the first and second electrodes.
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10.发明申请公开(公告)号：US20240414926A1
公开(公告)日：2024-12-12
申请号：US18813539
申请日：2024-08-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Wooyoung YANG , Bonwon KOO , Chungman KIM , Kwangmin PARK , Hajun SUNG , Dongho AHN , Changseung LEE , Minwoo CHOI
Abstract: A chalcogen compound layer exhibiting ovonic threshold switching characteristics, a switching device, a semiconductor device, and/or a semiconductor apparatus including the same are provided. The switching device and/or the semiconductor device may include two or more chalcogen compound layers having different energy band gaps. Alternatively, the switching device and/or semiconductor device may include a chalcogen compound layer having a concentration gradient of an element of boron (B), aluminum (Al), scandium (Sc), manganese (Mn), strontium (Sr), and/or indium (In) in a thickness direction thereof. The switching device and/or a semiconductor device may exhibit stable switching characteristics while having a low off-current value (leakage current value).
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