公开(公告)号：US20240324246A1

公开(公告)日：2024-09-26

申请号：US18594355

申请日：2024-03-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiyeon YANG ,  Donggeon GU ,  Bonwon KOO ,  Jeonghee PARK ,  Hajun SUNG ,  Dongho AHN ,  Zhe WU ,  Changseung LEE ,  Minwoo CHOI

IPC: H10B63/00 ,  H10N70/00

CPC classification number: H10B63/24 ,  H10B63/84 ,  H10N70/841 ,  H10N70/8825 ,  H10N70/8828

Abstract: Provided are a self-selecting memory device having polarity dependent threshold voltage shift characteristics and/or a memory apparatus including the self-selecting memory device. The memory device includes a first electrode, a second electrode apart from and facing the first electrode, and a memory layer between the first electrode and the second electrode. The memory layer has Ovonic threshold switching characteristics and is configured to have a threshold voltage of the memory layer be changed as a density of active traps in the memory layer is changed, the threshold voltage changing according to the polarity and the intensity of a bias voltage applied to the memory layer. Furthermore, an element composition distribution is configured to be maintained constant in the memory layer in response to the threshold voltage of the memory layer changing.

公开(公告)号：US20230230832A1

公开(公告)日：2023-07-20

申请号：US18095243

申请日：2023-01-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donggeon GU ,  Won-Jun LEE ,  Changyup PARK ,  Dongho AHN ,  Yewon KIM ,  Kwonyoung KIM ,  Okhyeon KIM

IPC: H01L21/02 ,  C23C16/455 ,  C23C16/06 ,  C23C16/56

CPC classification number: H01L21/02568 ,  H01L21/0262 ,  H01L21/02614 ,  C23C16/45527 ,  C23C16/06 ,  C23C16/56 ,  H10B63/10

Abstract: A method of forming a germanium antimony tellurium (GeSbTe) layer includes forming a germanium antimony (GeSb) layer by repeatedly performing a GeSb supercycle; and forming the GeSbTe layer by performing a tellurization operation on the GeSb layer, wherein the GeSb supercycle includes performing at least one GeSb cycle; and performing at least one Sb cycle, the GeSbTe has a composition of Ge2Sb2+aTe5+b, in which a and b satisfy the following relations: −0.2

公开(公告)号：US20230165001A1

公开(公告)日：2023-05-25

申请号：US17989061

申请日：2022-11-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwoo LEE ,  Jooheon KANG ,  Donggeon GU ,  Doyoon KIM ,  Yumin KIM ,  Suseong NOH ,  Changyup PARK ,  Hyunjae SONG ,  Dongho AHN ,  Myunghun WOO

IPC: H10B43/27 ,  H01L23/528 ,  H10B41/10 ,  H10B41/35 ,  H10B41/27 ,  H10B43/10 ,  H10B43/35

CPC classification number: H01L27/11582 ,  H01L23/5283 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157

Abstract: A semiconductor device includes a lower structure, a stack structure including gate layers and interlayer insulating layers alternately stacked on the lower structure in a first direction, and a channel structure in a channel hole passing through the stack structure. The channel structure includes a variable resistance material layer in the channel hole, a data storage material layer between the variable resistance material layer and a sidewall of the channel hole, and a channel layer between the data storage material layer and the sidewall of the channel hole, the channel layer includes a first element, the variable resistance material layer includes a second element, different from the first element, oxygen, and oxygen vacancies, and the data storage material layer includes the first element, the second element, oxygen, and oxygen vacancies.