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    RESISTIVE MEMORY DEVICE
    3.
    发明申请
    RESISTIVE MEMORY DEVICE 有权

    公开(公告)号：US20220406844A1

    公开(公告)日：2022-12-22

    申请号：US17568866

    申请日：2022-01-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Chungman KIM ,  Bonwon KOO ,  Dongho AHN ,  Kiyeon YANG ,  Zhe WU ,  Chang Seung LEE

    IPC: H01L27/24 ,  H01L45/00

    Abstract: A resistive memory device including a resistive memory pattern; and a selection element pattern electrically connected to the resistive memory pattern, the selection element pattern including a chalcogenide switching material and at least one metallic material, the chalcogenide switching material including germanium, arsenic, and selenium, and the at least one metallic material including aluminum, strontium, or indium, wherein the selection element pattern includes an inhomogeneous material layer in which content of the at least one metallic material in the selection element pattern is variable according to a position within the selection element pattern.

    VARIABLE RESISTANCE MEMORY DEVICE
    6.
    发明申请
    VARIABLE RESISTANCE MEMORY DEVICE 审中-公开

    公开(公告)号：US20200227475A1

    公开(公告)日：2020-07-16

    申请号：US16567094

    申请日：2019-09-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jeonghee PARK ,  Dongho AHN ,  Changyup PARK ,  Zhe WU

    IPC: H01L27/24 ,  H01L45/00

    Abstract: A variable resistance memory device including insulating patterns sequentially stacked on a substrate; first conductive lines between adjacent ones of the insulating patterns and spaced apart from each other in a first direction; a second conductive line between the first conductive lines and penetrating the insulating patterns in a third direction perpendicular to a top surface of the substrate; a phase-change pattern between the second conductive line and each of the first conductive lines and between the adjacent ones of the insulating patterns to cover a top surface of a first adjacent insulating pattern and a bottom surface of a second adjacent insulating pattern; and a selection element between the phase-change pattern and the second conductive line and between the adjacent ones of the insulating patterns to cover the top surface of the first adjacent insulating pattern and the bottom surface of the second adjacent insulating pattern.

    SEMICONDUCTOR DEVICE
    7.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220069011A1

    公开(公告)日：2022-03-03

    申请号：US17209660

    申请日：2021-03-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dongho AHN ,  Segab KWON ,  Chungman KIM ,  Kwangmin PARK ,  Zhe WU ,  Seunggeun YU ,  Wonjun LEE ,  Jabin LEE ,  Jinwoo LEE

    IPC: H01L27/24 ,  H01L45/00

    Abstract: A semiconductor device includes a semiconductor substrate, a peripheral device on the semiconductor substrate, a lower insulating structure on the semiconductor substrate and covering the peripheral device, a first conductive line on the lower insulating structure, a memory cell structure on the first conductive line, and a second conductive line on the memory cell structure. The memory cell structure may include an information storage material pattern and a selector material pattern on the lower insulating structure in a vertical direction. The selector material pattern may include a first selector material layer including a first material and a second selector material layer including a second material. The second selector material layer may have a threshold voltage drift higher than that of the first material. The second selector material layer may have a second width narrower than a first width of the first selector material layer.

    MEMORY DEVICE, MEMORY CELL AND METHOD FOR PROGRAMMING MEMORY CELL
    8.
    发明申请
    MEMORY DEVICE, MEMORY CELL AND METHOD FOR PROGRAMMING MEMORY CELL 审中-公开

    公开(公告)号：US20200152264A1

    公开(公告)日：2020-05-14

    申请号：US16530517

    申请日：2019-08-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Zhe WU ,  Ja Bin LEE ,  Jin Woo LEE ,  Kyu Bong JUNG

    IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24

    Abstract: A memory device includes a word line, a bit line intersecting the word line, and a memory cell at an intersection of the word line and the bit line. The memory cell includes a first electrode connected to the word line; a second electrode connected to the bit line; and a selective element layer between the first electrode and the second electrode. The selective element layer includes one of Ge—Se—Te, Ge—Se—Te—As, and Ge—Se—Te—As—Si, and a composition ratio of arsenic (As) component of each of the Ge—Se—Te—As and the Ge—Se—Te—As—Si being greater than 0.01 and less than 0.17.

    SEMICONDUCTOR MEMORY DEVICES
    9.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES 有权

    公开(公告)号：US20250006636A1

    公开(公告)日：2025-01-02

    申请号：US18651142

    申请日：2024-04-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Gwang Guk AN ,  Jun Ho SONG ,  Zhe WU ,  So Yeon CHOI

    IPC: H01L23/528 ,  H10B63/00 ,  H10N70/00

    Abstract: A semiconductor memory device comprising: a substrate extending in a first direction and a second direction; first conductive lines extending in the first direction on the substrate; first insulating structures that are alternately arranged with the first conductive lines in the second direction, wherein the first insulating structures extend in a third direction intersecting the first direction and the second direction; first information storage films on the first conductive lines and the first insulating structures; and second conductive lines extending in the second direction on the first information storage films, wherein the first information storage films include first regions that overlap the first conductive lines in the third direction and second regions that overlap the first insulating structures in the third direction, and a first height of upper surfaces of the first regions is different from a second height of upper surfaces of the second regions.

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