公开(公告)号：US20250029647A1

公开(公告)日：2025-01-23

申请号：US18407797

申请日：2024-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Siyeon Cho ,  Daewon Ha ,  Myunghun Woo

IPC: G11C11/22

Abstract: A method of operating a nonvolatile memory device includes applying a ground voltage to a selected wordline among the wordlines, applying an erase pass voltage to at least one unselected wordline among the wordlines, applying an erase voltage to a selected bitline among the bitlines, applying an erase prohibition voltage to an unselected bitline among the bitlines, and applying a Gate Induced Drain Leakage (GIDL) voltage to at least one string selection line corresponding to a string selected from among the plurality of strings.

公开(公告)号：US20220278273A1

公开(公告)日：2022-09-01

申请号：US17749289

申请日：2022-05-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YUKIO HAYAKAWA ,  Jooheon Kang ,  Myunghun Woo ,  Gunwook Yoon ,  Doohee Hwang

IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

Abstract: A vertical variable resistance memory device includes gate electrodes and a pillar structure. The gate electrodes are spaced apart from one another on a substrate in a vertical direction substantially perpendicular to an upper surface of the substrate. The pillar structure extends in the vertical direction through the gate electrodes on the substrate. The pillar structure includes a vertical gate electrode extending in the vertical direction, a variable resistance pattern disposed on a sidewall of the vertical gate electrode, and a channel disposed on an outer sidewall of the variable resistance pattern. The channel and the vertical gate electrode contact each other.

公开(公告)号：US10998334B2

公开(公告)日：2021-05-04

申请号：US16536842

申请日：2019-08-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bongyong Lee ,  Minkyung Bae ,  Myunghun Woo

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L23/522 ,  H01L21/225 ,  H01L21/3205

Abstract: A three-dimensional semiconductor memory device may include a stack including gate electrodes sequentially stacked on a substrate and a vertical structure penetrating the stack. The vertical structure may include a vertical channel portion, a charge storing structure on an outer side surface of the vertical channel portion, and a pad. The pad may include a first pad portion disposed in an internal space surrounded by the vertical channel portion and a second pad portion provided on the first pad portion and extended onto a top surface of the charge storing structure. A portion of the first pad portion may be disposed at the same level as an uppermost electrode of the gate electrodes.

公开(公告)号：US20240324239A1

公开(公告)日：2024-09-26

申请号：US18612011

申请日：2024-03-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daewon Ha ,  Kyunghwan Lee ,  Myunghun Woo

IPC: H10B53/30 ,  G11C5/06 ,  H01L21/28 ,  H01L29/51 ,  H01L29/78 ,  H10B51/10 ,  H10B51/30 ,  H10B53/10

CPC classification number: H10B53/30 ,  G11C5/063 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/78391 ,  H10B51/10 ,  H10B51/30 ,  H10B53/10

Abstract: A semiconductor memory device includes a plurality of memory cells each including a first vertical channel transistor (VCT) and a second VCT arranged in a vertical direction and connected to each other in series, the plurality of memory cells respectively including a plurality of ferroelectric capacitors connected to the second VCT in parallel and arranged in the vertical direction, wherein the plurality of memory cells are arranged in columns and rows in a first horizontal direction and a second horizontal direction that is different from the first horizontal direction.

公开(公告)号：US11114165B2

公开(公告)日：2021-09-07

申请号：US16821225

申请日：2020-03-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doohee Hwang ,  Taehun Kim ,  Minkyung Bae ,  Myunghun Woo ,  Bongyong Lee

IPC: G11C16/32 ,  G11C16/14 ,  G11C16/04 ,  G11C16/24 ,  G11C16/12 ,  G11C11/56 ,  H01L27/11582 ,  G11C16/08 ,  G11C16/16 ,  G11C16/30 ,  G11C5/06

Abstract: A semiconductor device includes a source layer; a plurality of channel structures; a plurality of gate electrodes; and a common source line. At least one of the plurality of gate electrodes provides a GIDL line. For an erasing operation, an erasing voltage applied to the common source line reaches a target voltage, and, after the erasing voltage reaches the target voltage, a step increment voltage is applied to the erasing voltage, such that the erasing voltage has a voltage level higher than a voltage level of the target voltage. After the step increment voltage has been applied for a desired time period, the voltage level of the erasing voltage is decreased to the target voltage level for the remainder of the erasing operation.

公开(公告)号：US10923195B2

公开(公告)日：2021-02-16

申请号：US16686327

申请日：2019-11-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minkyung Bae ,  Tae Hun Kim ,  Myunghun Woo ,  Bongyong Lee ,  Doohee Hwang

IPC: G11C11/34 ,  G11C16/14 ,  G11C16/08 ,  G11C16/04 ,  H01L27/11582

Abstract: An operating method of a nonvolatile memory device which includes a cell string including a plurality of cell transistors connected in series between a bit line and a common source line and stacked in a direction perpendicular to a substrate, the method including: programming an erase control transistor of the plurality of cell transistors; and after the erase control transistor is programmed, applying an erase voltage to the common source line or the bit line and applying an erase control voltage to an erase control line connected to the erase control transistor, wherein the erase control voltage is less than the erase voltage and greater than a ground voltage, and wherein the erase control transistor is between a ground selection transistor of the plurality of cell transistors and the common source line or between a string selection transistor of the plurality of cell transistors and the bit line.

公开(公告)号：US20240215250A1

公开(公告)日：2024-06-27

申请号：US18340419

申请日：2023-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seyun KIM ,  Jooheon Kang ,  Yumin Kim ,  Garam Park ,  Hyunjae Song ,  Dongho Ahn ,  Seungyeul Yang ,  Myunghun Woo ,  Jinwoo Lee ,  Seungdam Hyun

IPC: H10B43/35 ,  G11C16/04 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B43/35 ,  G11C16/0483 ,  H10B43/10 ,  H10B43/27

Abstract: A memory device including the vertical stack structure includes a gate electrode, a resistance change layer, a channel between the gate electrode and the resistance change layer, and an island structure between the resistance change layer and the channel and in contact with the resistance change layer and the channel, and a gate insulating layer between the gate electrode and the channel.

公开(公告)号：US20240172457A1

公开(公告)日：2024-05-23

申请号：US18497027

申请日：2023-10-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngji Noh ,  Jongho Woo ,  Jooheon Kang ,  Kyunghoon Kim ,  Myunghun Woo

IPC: H10B63/00

CPC classification number: H10B63/845 ,  H10B63/34

Abstract: A vertical memory device may include a cell stacked structure on a substrate, wherein the cell stacked structure includes an insulation layer pattern and a gate pattern are alternately and repeatedly stacked, and wherein the cell stacked structure extends in a first direction parallel to an upper surface of the substrate, and wherein an edge portion in the first direction of the cell stacked region is disposed in the second region and has a step portion having a step shape; an etch stop structure on an upper surface of each of gate patterns of the step portion of the cell stacked structure, wherein the etch stop structure includes a transition metal oxide; an insulating interlayer covering the cell stacked structure; and a contact plug passing through the insulating interlayer and the etch stop structure, wherein the contact plug contacts the upper surface of each of the gate patterns.

公开(公告)号：US11957071B2

公开(公告)日：2024-04-09

申请号：US17749289

申请日：2022-05-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yukio Hayakawa ,  Jooheon Kang ,  Myunghun Woo ,  Gunwook Yoon ,  Doohee Hwang

IPC: G11C13/00 ,  H10B63/00 ,  H10N70/00

CPC classification number: H10N70/826 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0038 ,  G11C13/0069 ,  H10B63/34 ,  H10N70/841 ,  H10N70/8833

Abstract: A vertical variable resistance memory device includes gate electrodes and a pillar structure. The gate electrodes are spaced apart from one another on a substrate in a vertical direction substantially perpendicular to an upper surface of the substrate. The pillar structure extends in the vertical direction through the gate electrodes on the substrate. The pillar structure includes a vertical gate electrode extending in the vertical direction, a variable resistance pattern disposed on a sidewall of the vertical gate electrode, and a channel disposed on an outer sidewall of the variable resistance pattern. The channel and the vertical gate electrode contact each other.

公开(公告)号：US20240065000A1

公开(公告)日：2024-02-22

申请号：US18169436

申请日：2023-02-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yumin Kim ,  Jooheon Kang ,  Sunho Kim ,  Seyun Kim ,  Garam Park ,  Hyunjae Song ,  Dongho Ahn ,  Seungyeul Yang ,  Myunghun Woo ,  Jinwoo Lee

IPC: H10B63/00 ,  G11C13/00 ,  G06N3/063

CPC classification number: H10B63/34 ,  G11C13/0007 ,  G11C13/003 ,  H10B63/845 ,  G06N3/063 ,  G11C2213/71 ,  G11C2213/75 ,  G11C2213/79

Abstract: Provided are a nonvolatile memory device and an operating method thereof. The nonvolatile memory device may include a conductive pillar, a resistance change layer surrounding a side surface of the conductive pillar, a semiconductor layer surrounding a side surface of the resistance change layer, a gate insulating layer surrounding a side surface of the semiconductor layer, and a plurality of insulating patterns and a plurality of gate electrodes alternately arranged along a surface of the gate insulating layer. The plurality of insulating patterns and the plurality of gate electrodes may surround a side surface of the gate insulating layer.