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    Three-dimensional semiconductor device and method of fabricating the same
    1.
    发明授权
    Three-dimensional semiconductor device and method of fabricating the same 有权

    公开(公告)号：US12218133B2

    公开(公告)日：2025-02-04

    申请号：US17805261

    申请日：2022-06-03

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sungil Park ,  Jae Hyun Park ,  Daewon Ha ,  Kyuman Hwang

    IPC: H01L29/78 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

    Abstract: Provided is a three-dimensional semiconductor device and its fabrication method. The semiconductor device includes a first active region on a substrate and including a plurality of lower channel patterns and a plurality of lower source/drain patterns that are alternately arranged along a first direction, a second active region on the first active region and including a plurality of upper channel patterns and a plurality of upper source/drain patterns that are alternately arranged along the first direction, a first gate electrode on a first lower channel pattern of the lower channel patterns and on a first upper channel pattern of the upper channel patterns, and a second gate electrode on a second lower channel pattern of the lower channel patterns and on a second upper channel pattern of the upper channel patterns. The second gate electrode may include lower and upper gate electrodes with an isolation pattern interposed therebetween.

    Semiconductor device
    2.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US12183741B2

    公开(公告)日：2024-12-31

    申请号：US18239241

    申请日：2023-08-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sungmin Kim ,  Daewon Ha

    IPC: H01L27/092 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L21/02

    Abstract: A semiconductor device includes an active pattern including a channel region. The channel region is disposed between first and second source/drain patterns that are spaced apart from each other in a first direction. The channel region is configured to connect the first and second source/drain patterns to each other. A gate electrode is disposed on a bottom surface of the active pattern and is disposed between the first and second source/drain patterns. An upper interconnection line is disposed on a top surface of the active pattern opposite to the bottom surface of the active pattern and is connected to the first source/drain pattern.

    SEMICONDUCTOR DEVICE
    3.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240064996A1

    公开(公告)日：2024-02-22

    申请号：US18170136

    申请日：2023-02-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kiheun Lee ,  Yongseok Kim ,  Hyuncheol Kim ,  Ilho Myeong ,  Daewon Ha

    IPC: H10B51/20 ,  H10B51/10 ,  H01L23/528 ,  H01L29/51 ,  H01L29/78

    CPC classification number: H10B51/20 ,  H10B51/10 ,  H01L23/5283 ,  H01L29/516 ,  H01L29/78391

    Abstract: A semiconductor device includes first and second cell arrays. The first cell array includes a first gate electrode that extends in a vertical direction, a first channel pattern on a side surface of the first gate electrode, and a first bit line electrically connected to the first channel pattern. The second cell array includes a second gate electrode that extends in the vertical direction, a second channel pattern on a side surface of the second gate electrode, and a second bit line electrically connected to the second channel pattern. A first bit line pad is electrically connected to the first bit line and a second bit line pad is electrically connected to the second bit line. The first bit line pad is spaced apart from the second bit line pad with the first and second cell arrays therebetween.

    FinFET semiconductor device and method of manufacturing the same
    6.
    发明授权
    FinFET semiconductor device and method of manufacturing the same 有权
    FinFET半导体器件及其制造方法

    公开(公告)号：US09130040B2

    公开(公告)日：2015-09-08

    申请号：US14248594

    申请日：2014-04-09

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： JaeHoo Park ,  Daewon Ha ,  Uihui Kwon ,  Sung-Dae Suk

    IPC: H01L29/78 ,  H01L29/66 ,  H01L27/092

    CPC classification number: H01L29/785 ,  H01L27/092 ,  H01L29/66795 ,  H01L29/7853

    Abstract: Provided are a semiconductor device and a method of manufacturing the same. The method of manufacturing a semiconductor device includes forming an active fin on a substrate; oxidizing a portion of the active fin to form an insulating pattern between the active fin and the substrate; forming a first gate pattern on the substrate, wherein the first gate pattern crosses the active fin; exposing the substrate on both sides of the first gate pattern; and forming source/drain regions on the exposed substrate.

    Abstract translation: 提供半导体器件及其制造方法。 制造半导体器件的方法包括：在衬底上形成有源散热片; 氧化活性鳍片的一部分以在活性鳍片和衬底之间形成绝缘图案; 在所述衬底上形成第一栅极图案，其中所述第一栅极图案与所述有源鳍片交叉; 在第一栅极图案的两侧上暴露衬底; 以及在暴露的衬底上形成源极/漏极区域。

    Semiconductor devices having multi-channel active regions and methods of forming same
    8.
    发明授权
    Semiconductor devices having multi-channel active regions and methods of forming same 有权

    公开(公告)号：US11798949B2

    公开(公告)日：2023-10-24

    申请号：US17712571

    申请日：2022-04-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Munhyeon Kim ,  Soonmoon Jung ,  Daewon Ha

    IPC: H01L27/12 ,  H01L29/08 ,  H01L21/84 ,  H01L29/423 ,  H01L29/10

    CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42356 ,  H01L29/42368

    Abstract: A multi-channel semiconductor-on-insulator (SOI) transistor includes a substrate having an electrically insulating layer thereon and a semiconductor active layer on the electrically insulating layer. A vertical stack of spaced-apart insulated gate electrodes, which are buried within the semiconductor active layer, is also provided. This vertical stack includes a first insulated gate electrode extending adjacent the electrically insulating layer and an (N−1)th insulated gate electrode that is spaced from a surface of the semiconductor active layer, where N is a positive integer greater than two. An Nth insulated gate electrode is provided on the surface of the semiconductor active layer. A pair of source/drain regions are provided within the semiconductor active layer. These source/drain regions extend adjacent opposing sides of the vertical stack of spaced-apart insulated gate electrodes. In some of these aspects, the semiconductor active layer extends between the pair of source/drain regions and the electrically insulating layer, whereas the first insulated gate electrode contacts the electrically insulating layer.

    Semiconductor Memory Device
    10.
    发明公开
    Semiconductor Memory Device 审中-公开

    公开(公告)号：US20230309317A1

    公开(公告)日：2023-09-28

    申请号：US18059010

    申请日：2022-11-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyuncheol KIM ,  Yongseok Kim ,  Kiheun Lee ,  Sangkil Lee ,  Daewon Ha

    IPC: H10B53/20 ,  H10B53/10 ,  H01L23/528

    CPC classification number: H01L27/11514 ,  H01L27/11504 ,  H01L23/5283

    Abstract: A semiconductor memory device is provided. The semiconductor memory device may include a semiconductor substrate; a data storage layer including capacitors disposed on the semiconductor substrate; a switching element layer on the data storage layer and including transistors connected to the respective capacitors; and a wiring layer on the switching element layer and including bit lines connected to the transistors, The respective transistors include an active pattern, a word line that crosses the active pattern such that the word line surrounds a first sidewall, a second sidewall and a top surface of the active pattern, and a ferroelectric layer between the word line and the active patter.

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