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公开(公告)号：US20230269941A1
公开(公告)日：2023-08-24
申请号：US18095576
申请日：2023-01-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Bongyong Lee , Yukio Hayakawa , Taeyoung Kim , Hyunmog Park , Siyeon Cho
CPC classification number: H10B43/27 , H10B43/35 , H10B43/10 , H10B41/10 , H10B41/27 , H10B41/35 , G11C16/14
Abstract: A semiconductor device includes a source structure, gate electrodes spaced apart from each other and stacked in a first direction, perpendicular to an upper surface of the source structure, and a channel structure extending through the gate electrodes in the first direction, and including a dielectric layer, a charge storage layer, a tunneling layer, a channel layer, and a buried semiconductor layer. The dielectric layer is between the gate electrodes and the charge storage layer. The tunneling layer is between charge storage layer and the channel layer. The channel layer is between the tunneling layer and the buried semiconductor layer. An outer surface of a lower portion of the channel layer is in contact with the source structure, and the dielectric layer includes a ferroelectric material, the channel layer includes an oxide semiconductor material, and the buried semiconductor layer includes silicon (Si).
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公开(公告)号：US20250029647A1
公开(公告)日：2025-01-23
申请号：US18407797
申请日：2024-01-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Siyeon Cho , Daewon Ha , Myunghun Woo
IPC: G11C11/22
Abstract: A method of operating a nonvolatile memory device includes applying a ground voltage to a selected wordline among the wordlines, applying an erase pass voltage to at least one unselected wordline among the wordlines, applying an erase voltage to a selected bitline among the bitlines, applying an erase prohibition voltage to an unselected bitline among the bitlines, and applying a Gate Induced Drain Leakage (GIDL) voltage to at least one string selection line corresponding to a string selected from among the plurality of strings.
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公开(公告)号：US20230320101A1
公开(公告)日：2023-10-05
申请号：US18153630
申请日：2023-01-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yukio HAYAKAWA , Bongyong Lee , Hyunmog Park , Siyeon Cho
Abstract: A semiconductor memory device includes a back gate electrode, a gate electrode on the back gate electrode, a channel layer between the gate electrode and the back gate electrode, a gate insulating layer between the channel layer and the gate electrode, and a ferroelectric layer between the back gate electrode and the channel layer.
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公开(公告)号：US20240015978A1
公开(公告)日：2024-01-11
申请号：US18320816
申请日：2023-05-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： Siyeon Cho , Taeyoung Kim , Hyunmog Park , Bongyong Lee , Yukio Hayakawa
IPC: H10B51/20 , H10B51/10 , H01L23/528
CPC classification number: H10B51/20 , H10B51/10 , H01L23/5283
Abstract: Disclosed are semiconductor memory devices and electronic systems including the same. The semiconductor memory device may include a vertical channel perpendicular to a top surface of a substrate, word lines disposed on a first side of the vertical channel and vertically stacked on the substrate, back-gate electrodes disposed on a second side of the vertical channel and vertically stacked on the substrate, a ferroelectric layer disposed between the word lines and the first side of the vertical channel, a first intermediate insulating layer disposed between the ferroelectric layer and the first side of the vertical channel, and a second intermediate insulating layer disposed between the back-gate electrodes and the second side of the vertical channel.
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公开(公告)号：US10930672B2
公开(公告)日：2021-02-23
申请号：US16524439
申请日：2019-07-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Siyeon Cho , Hyeri Shin , Sung-Bok Lee , Yusik Choi , Sungyung Hwang
IPC: H01L27/11582 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L23/528 , H01L27/24 , H01L27/22 , H01L23/535
Abstract: A three-dimensional (3D) semiconductor memory device includes a substrate including a cell array region, a connection region, and a block selection region between the cell array and connection regions, a stack structure including horizontal layers vertically stacked on the substrate, each of the horizontal layers including electrode portions extending in a first direction on the cell array and block selection regions and a connecting portion disposed on the connection region to connect the electrode portions in a second direction perpendicular to the first direction, and block selection gate electrodes intersecting sidewalls of the electrode portions of the horizontal layers on the block selection region. Each of the electrode portions includes a first semiconductor region having a first conductivity type on the cell array region and includes a channel dopant region having a second conductivity type different from the first conductivity type on the block selection region.
