A semiconductor memory device includes a plurality of memory cells each including a first vertical channel transistor (VCT) and a second VCT arranged in a vertical direction and connected to each other in series, the plurality of memory cells respectively including a plurality of ferroelectric capacitors connected to the second VCT in parallel and arranged in the vertical direction, wherein the plurality of memory cells are arranged in columns and rows in a first horizontal direction and a second horizontal direction that is different from the first horizontal direction.