公开(公告)号：US20230179418A1

公开(公告)日：2023-06-08

申请号：US17898045

申请日：2022-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungwoo Noh ,  Jisoo Kim ,  Kyungjin Lee ,  Younghyun Ji

IPC: H04L9/32 ,  H04L9/06 ,  H04L9/08

CPC classification number: H04L9/3213 ,  H04L9/0643 ,  H04L9/0861 ,  H04L9/3247

Abstract: A storage device includes a memory device storing data, and a controller controlling the memory device. The controller obtains and stores a certificate including a public key of an administrator from a host device, provides a nonce to the host device in response to a request from the host device, receives a token request signature including the nonce, a user identifier (ID), an allowed command list and a lifetime from the host device, and when it is verified that the token request signature is generated by a legitimate administrator by decrypting the token request signature with the public key, generates a token for allowing a user corresponding to the user ID to execute a command included in the allowed command list during the lifetime, and a token secret key corresponding to the token, and provides the token and the token secret key to the host device.

公开(公告)号：US20230170912A1

公开(公告)日：2023-06-01

申请号：US17964377

申请日：2022-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Baekmin LIM ,  Seungjin KIM ,  Seunghyun OH

IPC: H03L7/197 ,  H03L7/081 ,  H03L7/093

CPC classification number: H03L7/1976 ,  H03L7/081 ,  H03L7/093

Abstract: A fractional divider processing circuitry is to receive one of a plurality of clock signals as an input clock signal, and generate a first division clock signal based on the input clock signal and a first control signal. Phases of the plurality of clock signals partially overlap each other. The processing circuitry generates a delta-sigma modulation signal based on the first division clock signal and a frequency control word, and generates a second division clock signal based on the plurality of clock signals, the first division clock signal and a second control signal. The second control signal corresponds to a quantization noise of the delta-sigma modulation signal. The processing circuitry generates the second control signal and a digital control word based on the quantization noise of the delta-sigma modulator. The processing circuitry generates a final division clock signal based on the second division clock signal and the digital control word.

公开(公告)号：US20230200053A1

公开(公告)日：2023-06-22

申请号：US17945235

申请日：2022-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yangdoo Kim ,  Yonghwan Kim ,  Sangwuk Park ,  Sunghyun Park ,  Jinyoung Park ,  Minkyu Suh ,  Jungpyo Hong

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/34 ,  H10B12/033

Abstract: A semiconductor memory device includes a substrate including a memory cell region, a plurality of capacitor structures arranged in the memory cell region of the substrate and including a plurality of lower electrodes, a capacitor dielectric layer, and an upper electrode, a first support pattern contacting sidewalls of the plurality of lower electrodes of the plurality of capacitor structures to support the plurality of lower electrodes, and a second support pattern located at a higher vertical level than a vertical level of the first support pattern and contacting the sidewalls of the plurality of lower electrodes to support the plurality of lower electrodes. The plurality of lower electrodes have a plurality of recessed electrode portions, respectively, in upper portions of the plurality of lower electrodes.

公开(公告)号：US20250072106A1

公开(公告)日：2025-02-27

申请号：US18435305

申请日：2024-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jisoo PARK ,  Byungju KANG ,  Jaehyoung LIM ,  Kwanyoung CHUN ,  Subin CHOI

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A three-dimensional semiconductor device may include a back-side metal layer, a lower channel pattern on the back-side metal layer, first and second lower source/drain patterns, which are spaced apart from each other in a first direction with the lower channel pattern interposed therebetween, the first lower source/drain pattern being connected to the lower channel pattern, an upper channel pattern on the lower channel pattern, a first upper source/drain pattern on the first lower source/drain pattern, the first upper source/drain pattern being connected to the upper channel pattern, a second upper source/drain pattern on the second lower source/drain pattern, and a wide via electrically connecting the first upper source/drain pattern to the second lower source/drain pattern. The wide via may include first and second via portions having first and second top surfaces, and here, the second top surface may be located at a level lower than the first top surface.

公开(公告)号：US20250072055A1

公开(公告)日：2025-02-27

申请号：US18944685

申请日：2024-11-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwanghee LEE ,  Sangwook KIM

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: The present disclosure relates to oxide semiconductor transistors, methods of manufacturing the same, and/or memory devices including the oxide semiconductor transistors. The oxide semiconductor transistor includes first and second compound layers provided on a substrate, a channel layer in contact with the first and second compound layers, a first electrode facing a portion of the channel layer, a second electrode facing the first compound layer with the channel layer therebetween, and a third electrode facing the second compound layer with the channel layer therebetween. An oxygen concentration of a region of the channel layer facing the first electrode is greater than that of the remaining regions of the channel layer. A buffer layer may further be provided between the channel layer and the second and third electrodes. The first and second compound layers may include oxygen and a metal.

公开(公告)号：US20250072001A1

公开(公告)日：2025-02-27

申请号：US18800667

申请日：2024-08-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hanbyeol LEE ,  Sukkang SUNG ,  Younghwan SON

IPC: H10B43/40 ,  G11C16/04 ,  H01L23/528 ,  H01L23/532 ,  H01L25/065 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B80/00

Abstract: A semiconductor device includes: a peripheral circuit structure including a substrate and a circuit that is disposed on the substrate; a cell structure disposed on the peripheral circuit structure and including gate electrodes and a channel that extends through the gate electrodes; and a bonding structure located between the peripheral circuit structure and the cell structure, wherein the bonding structure includes: a first insulating layer attached to the peripheral circuit structure; a first bonding pad disposed on the peripheral circuit structure and electrically connected to the circuit; a second insulating layer attached to the cell structure; a second bonding pad disposed on the cell structure and electrically connected to the gate electrodes; and an anisotropic conductive adhesive layer located between the first insulating layer and the second insulating layer and between the first bonding pad and the second bonding pad, and including a plurality of conductive particles.

公开(公告)号：US20250071991A1

公开(公告)日：2025-02-27

申请号：US18583121

申请日：2024-02-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangwoo HAN ,  Jongho WOO ,  Seung Min LEE ,  Moonkang CHOI

IPC: H10B43/27 ,  H01L25/065 ,  H10B43/10 ,  H10B43/35 ,  H10B51/10 ,  H10B51/20 ,  H10B80/00

Abstract: A semiconductor device includes a source structure comprising a first source layer, a second source layer on the first source layer, and a third source layer on the second source layer, a gate stack structure on the source structure, the gate stack structure with alternating insulating patterns and conductive patterns, and a memory channel structure penetrating the gate stack structure. The memory channel structure includes a channel layer and a memory layer surrounding the channel layer. The channel layer penetrates the memory layer and the second source layer, and a bottom surface of the channel layer is in contact with the source structure.

公开(公告)号：US20250071800A1

公开(公告)日：2025-02-27

申请号：US18727059

申请日：2023-01-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Miao ZHOU ,  Min WU ,  Feifei SUN

IPC: H04W72/563 ,  H04L1/1829 ,  H04W72/25

Abstract: The disclosure provides a method performed by a communication device in a communication system, comprising: receiving multiple sidelink control information (SCI) from other communication devices; when the multiple SCI indicate the same or partially overlapping resource, based on at least one of information about relationship between the communication device and the multiple SCI, received power information related to the multiple SCI, and information about priorities indicated by the multiple SCI, determining whether a conflict occurs on resources indicated by the multiple SCI.

公开(公告)号：US20250071709A1

公开(公告)日：2025-02-27

申请号：US18882196

申请日：2024-09-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yongjin KANG ,  Duhe JANG ,  Byungseok SOH ,  Hyungyong LEE ,  Chanho JUNG

IPC: H04W56/00 ,  G06F1/12

Abstract: An electronic device includes a communication circuit including a first interface and a second interface, a memory storing instructions, and a processor communicatively coupled with the communication circuit via the first interface or via the second interface. The processor is configured to execute the instructions to send, to the communication circuit via the first interface, a request for clock information of the communication circuit, receive, from the communication circuit via the first interface, the clock information of the communication circuit, receive, from the communication circuit via the second interface, an interrupt signal and first time information corresponding to the interrupt signal being generated, and generate clock information of the processor based on the clock information of the communication circuit and the first time information.

公开(公告)号：US20250071667A1

公开(公告)日：2025-02-27

申请号：US18811538

申请日：2024-08-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mahmoud WATFA ,  Lalith KUMAR

IPC: H04W48/16 ,  H04W72/21

Abstract: The disclosure relates to a 5G or 6G communication system for supporting a higher data transmission rate. A method performed by a user equipment (UE) in a wireless communication system is provided. The method comprises receiving, from a base station, a protocol data unit (PDU) session modification command message for a modification of a PDU session, in case that the PDU session modification command message includes an alternative single-network slice selection assistance information (S-NSSAI), setting an S-NSSAI for a PDU session establishment procedure to an S-NSSAI of the PDU session and transmitting, to the base station, a message for requesting a PDU session establishment for the PDU session establishment procedure, wherein the message includes the S-NSSAI of the PDU session.