公开(公告)号：US12087554B2

公开(公告)日：2024-09-10

申请号：US16905018

申请日：2020-06-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungyeon Kim ,  Jungpyo Hong ,  Kwangnam Kim ,  Hyungjun Kim ,  Jongwoo Sun

IPC: H01J37/32 ,  H01L21/67

CPC classification number: H01J37/32495 ,  H01J37/3211 ,  H01J37/32119 ,  H01J37/3244 ,  H01J37/32715 ,  H01J37/32743 ,  H01L21/67069 ,  H01J2237/334

Abstract: A substrate treating apparatus, including a process chamber having a bottom portion configured to secure a substrate while a substrate treating process is performed on the substrate; and a dielectric window arranged at an upper portion of the process chamber to define a process space, and including: an insulative body, an antenna disposed on an upper surface of the insulative body, a protection layer disposed on a lower surface of the insulative body, and an etch resistor protruding from at least a portion of the protection layer toward the process space, wherein, based on power being applied to the antenna, a plasma is generated in the process space, and wherein the insulative body is protected from the plasma by the protection layer and the etch resistor.

公开(公告)号：US20240387168A1

公开(公告)日：2024-11-21

申请号：US18624788

申请日：2024-04-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinwoo Park ,  Heeyeop Chae ,  Yongjae Kim ,  Sangwuk Park ,  Yuna Lee ,  Jihye Lee ,  Jungpyo Hong

IPC: H01L21/02 ,  C23C16/44 ,  H01L21/311

Abstract: A method of manufacturing a semiconductor element includes placing a structure, the structure including a substrate and a first metal-containing film disposed on the substrate, fluorinating at least one atomic layer from an exposed surface of the first metal-containing film by supplying a fluorinating gas to the structure to form a fluorinated atomic layer, and etching the fluorinated atomic layer of the first metal-containing film by supplying an etching gas to the structure, wherein the etching gas includes an inert gas in a plasma state.

公开(公告)号：US20240074149A1

公开(公告)日：2024-02-29

申请号：US18312795

申请日：2023-05-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yangdoo KIM ,  Dongwook Kim ,  Sangwuk Park ,  Minkyu Suh ,  Geonyeop Lee ,  Dokeun Lee ,  Jungpyo Hong

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/0335

Abstract: An integrated circuit (IC) device may include a conductive area on a substrate; a first electrode connected to the conductive area on the substrate, a width of the first electrode in a lateral direction gradually increasing toward the substrate; a second electrode on the substrate, the second electrode including a silicon germanium (SiGe) film, the SiGe film surrounding the first electrode; and a dielectric film between the first electrode and the second electrode. A content of a component of the SiGe film may vary according to a distance from the substrate.

公开(公告)号：US20230377889A1

公开(公告)日：2023-11-23

申请号：US18125873

申请日：2023-03-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanggyo Chung ,  Chanmi Lee ,  Seunghee Han ,  Jungpyo Hong

IPC: H01L21/033 ,  H01L21/311

CPC classification number: H01L21/0337 ,  H01L21/31144

Abstract: Provided is a method for manufacturing a semiconductor device, in which a mask layer, a buffer layer, and a first mandrel layer are sequentially stacked on a substrate including a first region and a second region. First mandrel patterns are formed on the buffer layer in the first region, and a second mandrel pattern covering the buffer layer in the second region is formed. A first spacer contacting side walls of the first mandrel pattern and the second mandrel pattern is formed on the buffer layer. The first mandrel patterns are removed. A buffer layer pattern and a preliminary mask pattern are formed on the substrate. The second mandrel pattern is removed. In addition, a mask pattern is formed. The buffer layer includes a material having lower electrical conductivity than the mask layer and having etching selectivity with respect to the mask layer.

公开(公告)号：US20230209802A1

公开(公告)日：2023-06-29

申请号：US18088370

申请日：2022-12-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yuna Lee ,  Sangwuk Park ,  Hyunchul Yoon ,  Seungjae Lee ,  Joonkyu Rhee ,  Chanmin Lee ,  Jungpyo Hong

IPC: H10B12/00

CPC classification number: H10B12/09 ,  H10B12/482 ,  H10B12/50

Abstract: A method of fabricating a semiconductor device includes forming an insulating layer and a peripheral structure on first and second regions of the substrate, forming first and second mask layers on the insulating layer and the peripheral structure, patterning the first and second mask layers to form first and second mask structures on the first and second regions, etching the insulating layer using the first and second mask structures as an etching mask, to form insulating patterns, forming a sacrificial layer in spaces between two adjacent insulating patterns on the first region, removing the second mask pattern on the first region by a dry etching process, forming an anti-oxidation layer on a surface of the second mask layer on the second region after removing the second mask pattern on the first region, and removing the second mask layer with the anti-oxidation layer by a wet etching process.

公开(公告)号：US11430679B2

公开(公告)日：2022-08-30

申请号：US16821415

申请日：2020-03-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwangnam Kim ,  Nohsung Kwak ,  Sungyeon Kim ,  Hyungjun Kim ,  Haejoong Park ,  Jongwoo Sun ,  Sangrok Oh ,  Ilyoung Han ,  Jungpyo Hong

IPC: H01L21/67 ,  H01L21/687 ,  H01L21/677 ,  H01L21/673

Abstract: A semiconductor manufacturing apparatus including at least one load module including a load port on which a substrate container is located, a plurality of substrates being mountable on the substrate container; at least one loadlock module including a loadlock chamber directly connected to the substrate container, the loadlock chamber interchangeably having atmospheric pressure and vacuum pressure, a first transfer robot within the loadlock chamber, and a substrate stage within the loadlock chamber, the plurality of substrates being mountable on the substrate stage; a transfer module including a transfer chamber connected to the loadlock chamber, a second transfer robot within the transfer chamber, and a substrate aligner within the transfer chamber; and at least one process module including at least one process chamber connected to the transfer module.

公开(公告)号：US09087789B2

公开(公告)日：2015-07-21

申请号：US13728277

申请日：2012-12-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： HanNa Cho ,  Dongseok Lee ,  Jungpyo Hong

IPC: H01L21/00 ,  H01L21/308 ,  H01L21/04 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3213 ,  H01L29/66 ,  H01L27/115 ,  H01L49/02

CPC classification number: H01L21/308 ,  H01L21/0337 ,  H01L21/04 ,  H01L21/31144 ,  H01L21/32137 ,  H01L27/11582 ,  H01L28/90 ,  H01L29/66545 ,  H01L29/66825

Abstract: Methods of manufacturing a semiconductor device are provided. The method may include forming an etch target layer on a substrate, forming a carbon layer doped with boron on the etch target layer, a top end portion of the carbon layer having a different boron concentration from a bottom end portion of the carbon layer, patterning the carbon layer to form at least one opening exposing the etch target layer, and etching the exposed etch target layer using the carbon layer as an etch mask.

Abstract translation: 提供制造半导体器件的方法。 该方法可以包括在衬底上形成蚀刻目标层，在蚀刻目标层上形成掺杂有硼的碳层，碳层的顶部部分与碳层的底端部分具有不同的硼浓度，图案化 所述碳层形成暴露所述蚀刻目标层的至少一个开口，以及使用所述碳层作为蚀刻掩模蚀刻所述暴露的蚀刻目标层。

公开(公告)号：US20240321940A1

公开(公告)日：2024-09-26

申请号：US18423647

申请日：2024-01-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungjun Kim ,  Sangwuk Park ,  Hyunchul Yoon ,  Jungpyo Hong

IPC: H01G4/30

CPC classification number: H01L28/60

Abstract: A semiconductor device including a substrate and a capacitor structure arranged on the substrate. The capacitor structure includes a plurality of lower electrodes extending in a vertical direction perpendicular to a surface of the substrate and spaced apart from each other, supporters arranged between the plurality of lower electrodes, an upper electrode spaced apart from each of the plurality of lower electrodes, a dielectric layer arranged between each of the lower electrodes and the upper electrode, and a plurality of particles each in contact with the dielectric layer and arranged between each of the plurality of lower electrodes and the upper electrode.

公开(公告)号：US20240224502A1

公开(公告)日：2024-07-04

申请号：US18527450

申请日：2023-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yangdoo Kim ,  Sangwuk Park ,  Minkyu Suh ,  Geonyeop Lee ,  Dokeun Lee ,  Jungpyo Hong

IPC: H10B12/00

CPC classification number: H10B12/315

Abstract: A semiconductor memory device includes a substrate having a memory cell region and a plurality of capacitor structures in the memory cell region of the substrate, each of the plurality of capacitor structures including a lower electrode, a capacitor dielectric layer, and an upper electrode, wherein the lower electrode includes a first lower electrode, a second lower electrode above the first lower electrode, and a connecting lower electrode connecting a top end of the first lower electrode to a bottom end of the second lower electrode, wherein the upper electrode includes a bent upper electrode overlapping the connecting lower electrode in a horizontal direction, and the bent upper electrode includes a bent portion.

公开(公告)号：US12272555B2

公开(公告)日：2025-04-08

申请号：US17938684

申请日：2022-10-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinyoung Park ,  Jungpyo Hong ,  Yangdoo Kim ,  Yonghwan Kim ,  Sangwuk Park

IPC: H01L21/033 ,  H01L21/027 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3213

Abstract: Methods of forming a semiconductor device may include: providing a substrate on which a layer is formed; forming a lower hard-mask layer, which includes silicon, on the layer; forming an upper hard-mask pattern, which includes oxide, on the lower hard-mask layer; forming a lower hard-mask pattern by etching the lower hard-mask layer using the upper hard-mask pattern as an etch mask and using an etching gas that includes a metal-chloride-based first gas and a nitride-based second gas; and forming a plurality of contact holes in the layer by etching the material layer using the lower hard-mask pattern as an etch mask.