Semiconductor processing equipment including electrostatic chuck for plasma processing

    公开(公告)号:US11862440B2

    公开(公告)日:2024-01-02

    申请号:US17373214

    申请日:2021-07-12

    Abstract: Semiconductor processing equipment and an electrostatic chuck include a semiconductor having: an upper electrode; a gas supplier connected to the upper electrode; and a substrate supporting structure spaced apart from the upper electrode to define a processing volume. The substrate supporting structure supports a substrate and includes: a lower electrode having a side area disposed outside a step formed at an outer perimeter portion of the lower electrode and a processing area disposed inside the step; a first plate disposed on the lower electrode; an attraction electrode disposed on the first plate; and a second plate disposed on the attraction plate. The second plate supports the substrate in a state in which the substrate is laid on an upper surface of the second plate. Each of the first plate and the second plate includes ceramic. The lower electrode has a maximum height at a central portion of the processing area.

    Conduit structure of electronic device and electronic device including the same

    公开(公告)号:US10819836B2

    公开(公告)日:2020-10-27

    申请号:US16387059

    申请日:2019-04-17

    Abstract: A conduit structure of an electronic device and an electronic device are provided. The conduit structure includes an inner structure including a front surface and a rear surface, wherein the front surface includes a first region configured to receive a display and a second region, which is a remaining area of the front surface of the inner structure; a receiver hole configured to penetrate the second region and to connect a receiver receiving space and an external space of the inner structure; a first through-hole configured to penetrate the first region and to connect the receiver receiving space and the front surface of the inner structure; a second through-hole, which is spaced apart from the first through-hole, configured to penetrate the first region and to connect the rear surface of the inner structure; and a flow path configured to connect the first through-hole and the second through-hole at the front surface of the inner structure.

    Electronic device including coupling structure

    公开(公告)号:US10203728B2

    公开(公告)日:2019-02-12

    申请号:US15387562

    申请日:2016-12-21

    Abstract: An electronic device having a first housing including a first surface and a second surface at a rear surface opposite of the first surface and a coupling structure disposed on the first surface. A second housing for coupling to the first housing has a third surface, a fourth surface opposite of the third surface, and a side member enclosing a space between the third and fourth surfaces. The coupling structure is connected to the side member when the second housing is coupled to the first housing, and the coupling structure comprises a recess and a moving member. When the second housing is coupled to the first housing, the moving member performs a pivotal movement about a shaft. A retainer system may enable the second housing to at least partially stay within the moving member at the recess when the second housing is not coupled to the first housing.

    SEMICONDUCTOR MEMORY DEVICE
    5.
    发明公开

    公开(公告)号:US20230165016A1

    公开(公告)日:2023-05-25

    申请号:US17934317

    申请日:2022-09-22

    CPC classification number: H01L27/228 H01L43/04 H01L43/06

    Abstract: A semiconductor memory device is disclosed. The semiconductor memory device may include a magnetic tunnel junction pattern, a spin-orbit torque (SOT) pattern in contact with a first portion of the magnetic tunnel junction pattern, a first transistor electrically connected to a second portion of the magnetic tunnel junction pattern and configured to be controlled by a first word line, and a second transistor electrically connected to a first end of the spin-orbit torque pattern and configured to be controlled by a second word line. An effective channel width of the first transistor may be different from an effective channel width of the second transistor.

    Collection optics system for spectrometer and Raman spectral system

    公开(公告)号:US10520438B2

    公开(公告)日:2019-12-31

    申请号:US16034609

    申请日:2018-07-13

    Abstract: A collection optics system for a spectrometer and a Raman spectral system including the collection optics system is provided. The collection optics system is configured to selectively collect a Raman signal from scattered light output from a target object, the collection optics system includes a non-imaging collection unit configured to collect the Raman signal and output the Raman signal, the non-imaging collection unit including an entrance surface on which the scattered light is incident and an exit surface through which the Raman signal is output, and a Raman filter provided on a portion of the entrance surface of the non-imaging collection unit and configured to block the scattered light including a fluorescence signal. Therefore, the collection optics system may suppress reception of the fluorescence signal of the scattered light and selectively collect the Raman signal.

    SEMICONDUCTOR DEVICE
    8.
    发明申请

    公开(公告)号:US20240413216A1

    公开(公告)日:2024-12-12

    申请号:US18808369

    申请日:2024-08-19

    Abstract: A semiconductor device may include an active pattern on a substrate, a source/drain pattern on the active pattern, a channel pattern connected to the source/drain pattern, a gate electrode on the channel pattern, an active contact on the source/drain pattern, a first lower interconnection line on the gate electrode, and a second lower interconnection line on the active contact and at the same level as the first lower interconnection line. The gate electrode may include an electrode body portion and an electrode protruding portion, wherein the electrode protruding portion protrudes from a top surface of the electrode body portion and is in contact with the first lower interconnection line thereon. The active contact may include a contact body portion and a contact protruding portion, wherein the contact protruding portion protrudes from a top surface of the contact body portion and is in contact with the second lower interconnection line thereon.

    Semiconductor device
    9.
    发明授权

    公开(公告)号:US12094940B2

    公开(公告)日:2024-09-17

    申请号:US17546213

    申请日:2021-12-09

    Abstract: A semiconductor device may include an active pattern on a substrate, a source/drain pattern on the active pattern, a channel pattern connected to the source/drain pattern, a gate electrode on the channel pattern, an active contact on the source/drain pattern, a first lower interconnection line on the gate electrode, and a second lower interconnection line on the active contact and at the same level as the first lower interconnection line. The gate electrode may include an electrode body portion and an electrode protruding portion, wherein the electrode protruding portion protrudes from a top surface of the electrode body portion and is in contact with the first lower interconnection line thereon. The active contact may include a contact body portion and a contact protruding portion, wherein the contact protruding portion protrudes from a top surface of the contact body portion and is in contact with the second lower interconnection line thereon.

    SEMICONDUCTOR MEMORY DEVICES
    10.
    发明公开

    公开(公告)号:US20230200053A1

    公开(公告)日:2023-06-22

    申请号:US17945235

    申请日:2022-09-15

    CPC classification number: H10B12/315 H10B12/34 H10B12/033

    Abstract: A semiconductor memory device includes a substrate including a memory cell region, a plurality of capacitor structures arranged in the memory cell region of the substrate and including a plurality of lower electrodes, a capacitor dielectric layer, and an upper electrode, a first support pattern contacting sidewalls of the plurality of lower electrodes of the plurality of capacitor structures to support the plurality of lower electrodes, and a second support pattern located at a higher vertical level than a vertical level of the first support pattern and contacting the sidewalls of the plurality of lower electrodes to support the plurality of lower electrodes. The plurality of lower electrodes have a plurality of recessed electrode portions, respectively, in upper portions of the plurality of lower electrodes.

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