公开(公告)号：US20240387168A1

公开(公告)日：2024-11-21

申请号：US18624788

申请日：2024-04-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinwoo Park ,  Heeyeop Chae ,  Yongjae Kim ,  Sangwuk Park ,  Yuna Lee ,  Jihye Lee ,  Jungpyo Hong

IPC: H01L21/02 ,  C23C16/44 ,  H01L21/311

Abstract: A method of manufacturing a semiconductor element includes placing a structure, the structure including a substrate and a first metal-containing film disposed on the substrate, fluorinating at least one atomic layer from an exposed surface of the first metal-containing film by supplying a fluorinating gas to the structure to form a fluorinated atomic layer, and etching the fluorinated atomic layer of the first metal-containing film by supplying an etching gas to the structure, wherein the etching gas includes an inert gas in a plasma state.

公开(公告)号：US20240074149A1

公开(公告)日：2024-02-29

申请号：US18312795

申请日：2023-05-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yangdoo KIM ,  Dongwook Kim ,  Sangwuk Park ,  Minkyu Suh ,  Geonyeop Lee ,  Dokeun Lee ,  Jungpyo Hong

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/0335

Abstract: An integrated circuit (IC) device may include a conductive area on a substrate; a first electrode connected to the conductive area on the substrate, a width of the first electrode in a lateral direction gradually increasing toward the substrate; a second electrode on the substrate, the second electrode including a silicon germanium (SiGe) film, the SiGe film surrounding the first electrode; and a dielectric film between the first electrode and the second electrode. A content of a component of the SiGe film may vary according to a distance from the substrate.

公开(公告)号：US20240321940A1

公开(公告)日：2024-09-26

申请号：US18423647

申请日：2024-01-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungjun Kim ,  Sangwuk Park ,  Hyunchul Yoon ,  Jungpyo Hong

IPC: H01G4/30

CPC classification number: H01L28/60

Abstract: A semiconductor device including a substrate and a capacitor structure arranged on the substrate. The capacitor structure includes a plurality of lower electrodes extending in a vertical direction perpendicular to a surface of the substrate and spaced apart from each other, supporters arranged between the plurality of lower electrodes, an upper electrode spaced apart from each of the plurality of lower electrodes, a dielectric layer arranged between each of the lower electrodes and the upper electrode, and a plurality of particles each in contact with the dielectric layer and arranged between each of the plurality of lower electrodes and the upper electrode.

公开(公告)号：US20240224502A1

公开(公告)日：2024-07-04

申请号：US18527450

申请日：2023-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yangdoo Kim ,  Sangwuk Park ,  Minkyu Suh ,  Geonyeop Lee ,  Dokeun Lee ,  Jungpyo Hong

IPC: H10B12/00

CPC classification number: H10B12/315

Abstract: A semiconductor memory device includes a substrate having a memory cell region and a plurality of capacitor structures in the memory cell region of the substrate, each of the plurality of capacitor structures including a lower electrode, a capacitor dielectric layer, and an upper electrode, wherein the lower electrode includes a first lower electrode, a second lower electrode above the first lower electrode, and a connecting lower electrode connecting a top end of the first lower electrode to a bottom end of the second lower electrode, wherein the upper electrode includes a bent upper electrode overlapping the connecting lower electrode in a horizontal direction, and the bent upper electrode includes a bent portion.

公开(公告)号：US20230209802A1

公开(公告)日：2023-06-29

申请号：US18088370

申请日：2022-12-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yuna Lee ,  Sangwuk Park ,  Hyunchul Yoon ,  Seungjae Lee ,  Joonkyu Rhee ,  Chanmin Lee ,  Jungpyo Hong

IPC: H10B12/00

CPC classification number: H10B12/09 ,  H10B12/482 ,  H10B12/50

Abstract: A method of fabricating a semiconductor device includes forming an insulating layer and a peripheral structure on first and second regions of the substrate, forming first and second mask layers on the insulating layer and the peripheral structure, patterning the first and second mask layers to form first and second mask structures on the first and second regions, etching the insulating layer using the first and second mask structures as an etching mask, to form insulating patterns, forming a sacrificial layer in spaces between two adjacent insulating patterns on the first region, removing the second mask pattern on the first region by a dry etching process, forming an anti-oxidation layer on a surface of the second mask layer on the second region after removing the second mask pattern on the first region, and removing the second mask layer with the anti-oxidation layer by a wet etching process.

公开(公告)号：US20210057417A1

公开(公告)日：2021-02-25

申请号：US17076025

申请日：2020-10-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minhee Cho ,  Junsoo Kim ,  Ho Lee ,  Chankyung Kim ,  Hei Seung Kim ,  Jaehong Min ,  Sangwuk Park ,  Woo Bin Song ,  Sang Woo Lee

IPC: H01L27/108

Abstract: A semiconductor device can include a semiconductor substrate and an active region in the semiconductor substrate, where the active region can include an oxide semiconductor material having a variable atomic concentration of oxygen. A first source/drain region can be in the active region, where the first source/drain region can have a first atomic concentration of oxygen in the oxide semiconductor material. A second source/drain region can be in the active region spaced apart from first source/drain region and a channel region can be in the active region between the first source/drain region and the second source/drain region, where the channel region can have a second atomic concentration of oxygen in the oxide semiconductor material that is less than the first atomic concentration of oxygen. A gate electrode can be on the channel region and extend between the first source/drain region and the second source/drain region.

公开(公告)号：US10854612B2

公开(公告)日：2020-12-01

申请号：US16185892

申请日：2018-11-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhee Cho ,  Junsoo Kim ,  Ho Lee ,  Chankyung Kim ,  Hei Seung Kim ,  Jaehong Min ,  Sangwuk Park ,  Woo Bin Song ,  Sang Woo Lee

IPC: H01L27/108

Abstract: A semiconductor device can include a semiconductor substrate and an active region in the semiconductor substrate, where the active region can include an oxide semiconductor material having a variable atomic concentration of oxygen. A first source/drain region can be in the active region, where the first source/drain region can have a first atomic concentration of oxygen in the oxide semiconductor material. A second source/drain region can be in the active region spaced apart from first source/drain region and a channel region can be in the active region between the first source/drain region and the second source/drain region, where the channel region can have a second atomic concentration of oxygen in the oxide semiconductor material that is less than the first atomic concentration of oxygen. A gate electrode can be on the channel region and extend between the first source/drain region and the second source/drain region.

公开(公告)号：US12272555B2

公开(公告)日：2025-04-08

申请号：US17938684

申请日：2022-10-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinyoung Park ,  Jungpyo Hong ,  Yangdoo Kim ,  Yonghwan Kim ,  Sangwuk Park

IPC: H01L21/033 ,  H01L21/027 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3213

Abstract: Methods of forming a semiconductor device may include: providing a substrate on which a layer is formed; forming a lower hard-mask layer, which includes silicon, on the layer; forming an upper hard-mask pattern, which includes oxide, on the lower hard-mask layer; forming a lower hard-mask pattern by etching the lower hard-mask layer using the upper hard-mask pattern as an etch mask and using an etching gas that includes a metal-chloride-based first gas and a nitride-based second gas; and forming a plurality of contact holes in the layer by etching the material layer using the lower hard-mask pattern as an etch mask.

公开(公告)号：US20240147698A1

公开(公告)日：2024-05-02

申请号：US18368635

申请日：2023-09-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Geonyeop Lee ,  Dongwook Kim ,  Yangdoo Kim ,  Sangki Nam ,  Sangwuk Park ,  Minkyu Suh ,  Dokeun Lee ,  Sungho Jang ,  Jungpyo Hong

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/0335

Abstract: A semiconductor device includes; a lower structure, lower electrodes on the lower structure, wherein each lower electrode includes a first lower electrode and a second lower electrode on the first lower electrode and electrically connected to the first lower electrode, an upper electrode covering the lower electrodes, and a dielectric film between the lower electrodes and the upper electrode, wherein the first lower electrode includes a pillar portion and a protruding portion on the pillar portion, wherein protruding portion has a complex shape that contacts the second lower electrode.

公开(公告)号：US11862476B2

公开(公告)日：2024-01-02

申请号：US17076025

申请日：2020-10-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minhee Cho ,  Junsoo Kim ,  Ho Lee ,  Chankyung Kim ,  Hei Seung Kim ,  Jaehong Min ,  Sangwuk Park ,  Woo Bin Song ,  Sang Woo Lee

IPC: H01L21/34 ,  H10B12/00 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L21/34 ,  H01L21/02 ,  H01L21/28 ,  H10B12/053 ,  H10B12/31 ,  H10B12/482

Abstract: A semiconductor device can include a semiconductor substrate and an active region in the semiconductor substrate, where the active region can include an oxide semiconductor material having a variable atomic concentration of oxygen. A first source/drain region can be in the active region, where the first source/drain region can have a first atomic concentration of oxygen in the oxide semiconductor material. A second source/drain region can be in the active region spaced apart from first source/drain region and a channel region can be in the active region between the first source/drain region and the second source/drain region, where the channel region can have a second atomic concentration of oxygen in the oxide semiconductor material that is less than the first atomic concentration of oxygen. A gate electrode can be on the channel region and extend between the first source/drain region and the second source/drain region.