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公开(公告)号：US10396083B2
公开(公告)日：2019-08-27
申请号：US15974943
申请日：2018-05-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Nam-Gun Kim , Joonkyu Rhee , Ji-Hye Lee , Chanmi Lee , Taeseop Choi
IPC: H01L21/768 , H01L27/108
Abstract: Example embodiments relate to a semiconductor device. The semiconductor device includes a substrate including an active region extending in a first direction, a plurality of bit lines running across the active region in a second direction crossing the first direction, a first spacer on a sidewall of the bit line, and a storage node contact on the active region between adjacent bit lines. The first spacer includes a first part between the storage node contact and the bit line, a second part between the first part and the storage node contact, and a third part between the first and second parts. A minimum vertical thickness of the first part is greater than a maximum vertical thickness of the third part. The maximum vertical thickness of the third part is greater than a maximum vertical thickness of the second part.
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公开(公告)号：US10153283B2
公开(公告)日：2018-12-11
申请号：US15433199
申请日：2017-02-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Nam-Gun Kim , Chanmi Lee , Joonkyu Rhee , Ji-Hye Lee , Taeseop Choi
IPC: H01L21/70 , H01L27/108 , H01L27/22 , H01L27/24
Abstract: Semiconductor devices and method of manufacturing the same are provided. The devices may include a substrate including a first impurity region and second impurity regions spaced apart from the first impurity region and a conductive line. The conductive line may extend in a first direction and may be electrically connected to the first impurity region. The devices may also include first conductive contacts on a side of the conductive line and arranged in the first direction and first insulation patterns on the side of the conductive line and arranged in the first direction. The first conductive contacts may be electrically connected to the second impurity regions. The first conductive contacts and the first insulation patterns may be alternately disposed along the first direction. Top surfaces of the first insulation patterns may be lower than a top surface of the conductive line relative to an upper surface of the substrate.
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公开(公告)号：US11716839B2
公开(公告)日：2023-08-01
申请号：US17357139
申请日：2021-06-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Joonkyu Rhee , Jiyoung Ahn , Hyunyong Kim , Jamin Koo , Yongseok Ahn , Minsub Um , Sangho Lee , Yoonyoung Choi
IPC: H10B12/00
CPC classification number: H10B12/315 , H10B12/34
Abstract: A semiconductor device includes an active pattern on a substrate, a gate structure buried at an upper portion of the active pattern, a bit line structure on the active pattern, a lower spacer structure covering a lower sidewall of the bit line structure, a contact plug structure on the active pattern and adjacent to the bit line structure, and a capacitor on the contact plug structure. The lower spacer structure includes first and second lower spacers that are sequentially stacked from the lower sidewall of the bit line structure in a horizontal direction that is substantially parallel to an upper surface of the substrate, the first lower spacer includes an oxide, and contacts the lower sidewall of the bit line structure, but does not contact the contact plug structure, and the second lower spacer includes a material different from any of the materials of the first lower spacer.
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公开(公告)号：US20230209802A1
公开(公告)日：2023-06-29
申请号：US18088370
申请日：2022-12-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yuna Lee , Sangwuk Park , Hyunchul Yoon , Seungjae Lee , Joonkyu Rhee , Chanmin Lee , Jungpyo Hong
IPC: H10B12/00
CPC classification number: H10B12/09 , H10B12/482 , H10B12/50
Abstract: A method of fabricating a semiconductor device includes forming an insulating layer and a peripheral structure on first and second regions of the substrate, forming first and second mask layers on the insulating layer and the peripheral structure, patterning the first and second mask layers to form first and second mask structures on the first and second regions, etching the insulating layer using the first and second mask structures as an etching mask, to form insulating patterns, forming a sacrificial layer in spaces between two adjacent insulating patterns on the first region, removing the second mask pattern on the first region by a dry etching process, forming an anti-oxidation layer on a surface of the second mask layer on the second region after removing the second mask pattern on the first region, and removing the second mask layer with the anti-oxidation layer by a wet etching process.
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公开(公告)号：US09142757B2
公开(公告)日：2015-09-22
申请号：US14492419
申请日：2014-09-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jongchul Park , Hyungjoon Kwon , Joonkyu Rhee
Abstract: A magnetic memory device may include a lower electrode on a substrate, a memory element on the lower electrode, an upper electrode on the memory element, and a protection spacer enclosing a portion of a side surface of the lower electrode and protruding laterally from the side surface of the lower electrode. The protection spacer may have a bottom surface that is positioned at a level higher than that of a bottom surface of the lower electrode.
Abstract translation: 磁存储器件可以包括衬底上的下电极，下电极上的存储元件，存储元件上的上电极，以及包围下电极的侧表面的一部分并从侧面侧向突出的保护间隔件 下电极的表面。 保护间隔件可以具有位于比下电极的底表面高的位置的底表面。
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Patent Agency Ranking
公开(公告)号：US12048143B2
公开(公告)日：2024-07-23
申请号：US17392775
申请日：2021-08-03
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jiyoung Ahn , Yongseok Ahn , Hyunyong Kim , Minsub Um , Ju Hyung We , Joonkyu Rhee , Yoonyoung Choi
IPC: H10B12/00
CPC classification number: H10B12/315 , H10B12/0335 , H10B12/053 , H10B12/34 , H10B12/482 , H10B12/485
Abstract: A semiconductor memory device includes a substrate including a device isolation pattern defining an active pattern extending in a first direction and including first and second source/drain regions, a word line extending in a second direction intersecting the first direction, a bit line that is on the word line and electrically connected to the first source/drain region and that extends in a third direction that intersects the first and second directions, a bit-line spacer on a sidewall of the bit line, a storage node contact electrically connected to the second source/drain region and spaced apart from the bit line across the bit-line spacer, and a dielectric pattern between the bit-line spacer and the storage node contact. The bit-line spacer includes a first spacer covering the sidewall of the bit line and a second spacer between the dielectric pattern and the first spacer.
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公开(公告)号：US10573651B2
公开(公告)日：2020-02-25
申请号：US16422054
申请日：2019-05-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Nam-Gun Kim , Joonkyu Rhee , Ji-Hye Lee , Chanmi Lee , Taeseop Choi
IPC: H01L27/108 , H01L21/768
Abstract: Example embodiments relate to a semiconductor device. The semiconductor device includes a substrate including an active region extending in a first direction, a plurality of bit lines running across the active region in a second direction crossing the first direction, a first spacer on a sidewall of the bit line, and a storage node contact on the active region between adjacent bit lines. The first spacer includes a first part between the storage node contact and the bit line, a second part between the first part and the storage node contact, and a third part between the first and second parts. A minimum vertical thickness of the first part is greater than a maximum vertical thickness of the third part. The maximum vertical thickness of the third part is greater than a maximum vertical thickness of the second part.
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公开(公告)号：US20180261601A1
公开(公告)日：2018-09-13
申请号：US15974943
申请日：2018-05-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Nam-Gun KIM , Joonkyu Rhee , Ji-Hye Lee , Chanmi Lee , Taeseop Choi
IPC: H01L27/108 , H01L21/768
CPC classification number: H01L27/10814 , H01L21/7682 , H01L21/76897 , H01L27/10823 , H01L27/10855 , H01L27/10885 , H01L27/10888
Abstract: Example embodiments relate to a semiconductor device. The semiconductor device includes a substrate including an active region extending in a first direction, a plurality of bit lines running across the active region in a second direction crossing the first direction, a first spacer on a sidewall of the bit line, and a storage node contact on the active region between adjacent bit lines. The first spacer includes a first part between the storage node contact and the bit line, a second part between the first part and the storage node contact, and a third part between the first and second parts. A minimum vertical thickness of the first part is greater than a maximum vertical thickness of the third part. The maximum vertical thickness of the third part is greater than a maximum vertical thickness of the second part.
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公开(公告)号：US09997521B2
公开(公告)日：2018-06-12
申请号：US15405808
申请日：2017-01-13
Applicant: Samsung Electronics Co., Ltd.
Inventor： Nam-Gun Kim , Joonkyu Rhee , Ji-Hye Lee , Chanmi Lee , Taeseop Choi
IPC: H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119 , H01L21/768
CPC classification number: H01L27/10814 , H01L21/7682 , H01L27/10823 , H01L27/10855 , H01L27/10885 , H01L27/10888
Abstract: Example embodiments relate to a semiconductor device. The semiconductor device includes a substrate including an active region extending in a first direction, a plurality of bit lines running across the active region in a second direction crossing the first direction, a first spacer on a sidewall of the bit line, and a storage node contact on the active region between adjacent bit lines. The first spacer includes a first part between the storage node contact and the bit line, a second part between the first part and the storage node contact, and a third part between the first and second parts. A minimum vertical thickness of the first part is greater than a maximum vertical thickness of the third part. The maximum vertical thickness of the third part is greater than a maximum vertical thickness of the second part.
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公开(公告)号：US20170294439A1
公开(公告)日：2017-10-12
申请号：US15433199
申请日：2017-02-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Nam-Gun KIM , Chanmi Lee , Joonkyu Rhee , Ji-Hye Lee , Taeseop Choi
IPC: H01L27/108
CPC classification number: H01L27/10805 , H01L27/10814 , H01L27/10823 , H01L27/10852 , H01L27/10876 , H01L27/10882 , H01L27/10885 , H01L27/228 , H01L27/2436
Abstract: Semiconductor devices and method of manufacturing the same are provided. The devices may include a substrate including a first impurity region and second impurity regions spaced apart from the first impurity region and a conductive line. The conductive line may extend in a first direction and may be electrically connected to the first impurity region. The devices may also include first conductive contacts on a side of the conductive line and arranged in the first direction and first insulation patterns on the side of the conductive line and arranged in the first direction. The first conductive contacts may be electrically connected to the second impurity regions. The first conductive contacts and the first insulation patterns may be alternately disposed along the first direction. Top surfaces of the first insulation patterns may be lower than a top surface of the conductive line relative to an upper surface of the substrate.
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