公开(公告)号：US20230377889A1

公开(公告)日：2023-11-23

申请号：US18125873

申请日：2023-03-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanggyo Chung ,  Chanmi Lee ,  Seunghee Han ,  Jungpyo Hong

IPC: H01L21/033 ,  H01L21/311

CPC classification number: H01L21/0337 ,  H01L21/31144

Abstract: Provided is a method for manufacturing a semiconductor device, in which a mask layer, a buffer layer, and a first mandrel layer are sequentially stacked on a substrate including a first region and a second region. First mandrel patterns are formed on the buffer layer in the first region, and a second mandrel pattern covering the buffer layer in the second region is formed. A first spacer contacting side walls of the first mandrel pattern and the second mandrel pattern is formed on the buffer layer. The first mandrel patterns are removed. A buffer layer pattern and a preliminary mask pattern are formed on the substrate. The second mandrel pattern is removed. In addition, a mask pattern is formed. The buffer layer includes a material having lower electrical conductivity than the mask layer and having etching selectivity with respect to the mask layer.

公开(公告)号：US10396083B2

公开(公告)日：2019-08-27

申请号：US15974943

申请日：2018-05-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nam-Gun Kim ,  Joonkyu Rhee ,  Ji-Hye Lee ,  Chanmi Lee ,  Taeseop Choi

IPC: H01L21/768 ,  H01L27/108

Abstract: Example embodiments relate to a semiconductor device. The semiconductor device includes a substrate including an active region extending in a first direction, a plurality of bit lines running across the active region in a second direction crossing the first direction, a first spacer on a sidewall of the bit line, and a storage node contact on the active region between adjacent bit lines. The first spacer includes a first part between the storage node contact and the bit line, a second part between the first part and the storage node contact, and a third part between the first and second parts. A minimum vertical thickness of the first part is greater than a maximum vertical thickness of the third part. The maximum vertical thickness of the third part is greater than a maximum vertical thickness of the second part.

公开(公告)号：US10153283B2

公开(公告)日：2018-12-11

申请号：US15433199

申请日：2017-02-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nam-Gun Kim ,  Chanmi Lee ,  Joonkyu Rhee ,  Ji-Hye Lee ,  Taeseop Choi

IPC: H01L21/70 ,  H01L27/108 ,  H01L27/22 ,  H01L27/24

Abstract: Semiconductor devices and method of manufacturing the same are provided. The devices may include a substrate including a first impurity region and second impurity regions spaced apart from the first impurity region and a conductive line. The conductive line may extend in a first direction and may be electrically connected to the first impurity region. The devices may also include first conductive contacts on a side of the conductive line and arranged in the first direction and first insulation patterns on the side of the conductive line and arranged in the first direction. The first conductive contacts may be electrically connected to the second impurity regions. The first conductive contacts and the first insulation patterns may be alternately disposed along the first direction. Top surfaces of the first insulation patterns may be lower than a top surface of the conductive line relative to an upper surface of the substrate.

公开(公告)号：US10573651B2

公开(公告)日：2020-02-25

申请号：US16422054

申请日：2019-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nam-Gun Kim ,  Joonkyu Rhee ,  Ji-Hye Lee ,  Chanmi Lee ,  Taeseop Choi

IPC: H01L27/108 ,  H01L21/768

Abstract: Example embodiments relate to a semiconductor device. The semiconductor device includes a substrate including an active region extending in a first direction, a plurality of bit lines running across the active region in a second direction crossing the first direction, a first spacer on a sidewall of the bit line, and a storage node contact on the active region between adjacent bit lines. The first spacer includes a first part between the storage node contact and the bit line, a second part between the first part and the storage node contact, and a third part between the first and second parts. A minimum vertical thickness of the first part is greater than a maximum vertical thickness of the third part. The maximum vertical thickness of the third part is greater than a maximum vertical thickness of the second part.

公开(公告)号：US20180261601A1

公开(公告)日：2018-09-13

申请号：US15974943

申请日：2018-05-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nam-Gun KIM ,  Joonkyu Rhee ,  Ji-Hye Lee ,  Chanmi Lee ,  Taeseop Choi

IPC: H01L27/108 ,  H01L21/768

CPC classification number: H01L27/10814 ,  H01L21/7682 ,  H01L21/76897 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888

Abstract: Example embodiments relate to a semiconductor device. The semiconductor device includes a substrate including an active region extending in a first direction, a plurality of bit lines running across the active region in a second direction crossing the first direction, a first spacer on a sidewall of the bit line, and a storage node contact on the active region between adjacent bit lines. The first spacer includes a first part between the storage node contact and the bit line, a second part between the first part and the storage node contact, and a third part between the first and second parts. A minimum vertical thickness of the first part is greater than a maximum vertical thickness of the third part. The maximum vertical thickness of the third part is greater than a maximum vertical thickness of the second part.

公开(公告)号：US09997521B2

公开(公告)日：2018-06-12

申请号：US15405808

申请日：2017-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nam-Gun Kim ,  Joonkyu Rhee ,  Ji-Hye Lee ,  Chanmi Lee ,  Taeseop Choi

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119 ,  H01L21/768

CPC classification number: H01L27/10814 ,  H01L21/7682 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888

Abstract: Example embodiments relate to a semiconductor device. The semiconductor device includes a substrate including an active region extending in a first direction, a plurality of bit lines running across the active region in a second direction crossing the first direction, a first spacer on a sidewall of the bit line, and a storage node contact on the active region between adjacent bit lines. The first spacer includes a first part between the storage node contact and the bit line, a second part between the first part and the storage node contact, and a third part between the first and second parts. A minimum vertical thickness of the first part is greater than a maximum vertical thickness of the third part. The maximum vertical thickness of the third part is greater than a maximum vertical thickness of the second part.

公开(公告)号：US20170294439A1

公开(公告)日：2017-10-12

申请号：US15433199

申请日：2017-02-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nam-Gun KIM ,  Chanmi Lee ,  Joonkyu Rhee ,  Ji-Hye Lee ,  Taeseop Choi

IPC: H01L27/108

CPC classification number: H01L27/10805 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10876 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/228 ,  H01L27/2436

Abstract: Semiconductor devices and method of manufacturing the same are provided. The devices may include a substrate including a first impurity region and second impurity regions spaced apart from the first impurity region and a conductive line. The conductive line may extend in a first direction and may be electrically connected to the first impurity region. The devices may also include first conductive contacts on a side of the conductive line and arranged in the first direction and first insulation patterns on the side of the conductive line and arranged in the first direction. The first conductive contacts may be electrically connected to the second impurity regions. The first conductive contacts and the first insulation patterns may be alternately disposed along the first direction. Top surfaces of the first insulation patterns may be lower than a top surface of the conductive line relative to an upper surface of the substrate.