公开(公告)号：US11435981B2

公开(公告)日：2022-09-06

申请号：US16847872

申请日：2020-04-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghwan Kim ,  Wook Kim ,  Jaejoon Kim ,  Sungju Ryu

IPC: G06F7/501 ,  G06N3/063 ,  G06F7/57 ,  G06F7/523

Abstract: An arithmetic circuit includes an input buffer latching each of a plurality of input signals, sequentially input, and sequentially outputting a plurality of first addition signals and a plurality of second addition signals based on the plurality of input signals; a first ripple carry adder (RCA) performing a first part of an accumulation operation on the first addition signals to generate a carry; a flip-flop; a second RCA performing a second part of the accumulation operation on the second addition signals and an output of the flop-flop; the first RCA latching the carry in the flip-flop after the accumulation operation is performed; and an output buffer latching an output signal of the first RCA and an output signal of the second RCA, and outputting a sum signal representing a sum of the plurality of input signals.

公开(公告)号：US12272555B2

公开(公告)日：2025-04-08

申请号：US17938684

申请日：2022-10-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinyoung Park ,  Jungpyo Hong ,  Yangdoo Kim ,  Yonghwan Kim ,  Sangwuk Park

IPC: H01L21/033 ,  H01L21/027 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3213

Abstract: Methods of forming a semiconductor device may include: providing a substrate on which a layer is formed; forming a lower hard-mask layer, which includes silicon, on the layer; forming an upper hard-mask pattern, which includes oxide, on the lower hard-mask layer; forming a lower hard-mask pattern by etching the lower hard-mask layer using the upper hard-mask pattern as an etch mask and using an etching gas that includes a metal-chloride-based first gas and a nitride-based second gas; and forming a plurality of contact holes in the layer by etching the material layer using the lower hard-mask pattern as an etch mask.

公开(公告)号：US20230200053A1

公开(公告)日：2023-06-22

申请号：US17945235

申请日：2022-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yangdoo Kim ,  Yonghwan Kim ,  Sangwuk Park ,  Sunghyun Park ,  Jinyoung Park ,  Minkyu Suh ,  Jungpyo Hong

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/34 ,  H10B12/033

Abstract: A semiconductor memory device includes a substrate including a memory cell region, a plurality of capacitor structures arranged in the memory cell region of the substrate and including a plurality of lower electrodes, a capacitor dielectric layer, and an upper electrode, a first support pattern contacting sidewalls of the plurality of lower electrodes of the plurality of capacitor structures to support the plurality of lower electrodes, and a second support pattern located at a higher vertical level than a vertical level of the first support pattern and contacting the sidewalls of the plurality of lower electrodes to support the plurality of lower electrodes. The plurality of lower electrodes have a plurality of recessed electrode portions, respectively, in upper portions of the plurality of lower electrodes.

公开(公告)号：US20230171954A1

公开(公告)日：2023-06-01

申请号：US17965936

申请日：2022-10-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yangdoo Kim ,  Namgun Kim ,  Yonghwan Kim ,  Sangwuk Park ,  Minkyu Suh ,  Jungpyo Hong

IPC: H01L27/108

CPC classification number: H01L27/10897 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10894

Abstract: A semiconductor device includes a substrate having a cell array region and a peripheral region, lower electrodes disposed on the cell array region, at least one supporter layer contacting the lower electrodes, a dielectric layer covering the lower electrodes and the at least one supporter layer, an upper electrode covering the dielectric layer, an interlayer insulating layer covering an upper surface and a side surface of the upper electrode, a peripheral contact plug passing through the interlayer insulating layer on the peripheral region of the substrate, and a first oxide layer between the upper electrode and the peripheral contact plug. The upper electrode includes at least one protruding region protruding in a lateral direction from the cell array region toward the peripheral region. The first oxide layer is disposed between the at least one protrusion region and the peripheral contact plug.