公开(公告)号：US11107906B2

公开(公告)日：2021-08-31

申请号：US16798482

申请日：2020-02-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang Woo Sohn ,  Seung Hyun Song ,  Seon-Bae Kim ,  Min Cheol Oh ,  Young Chai Jung

IPC: H01L29/66

Abstract: Integrated circuit devices and methods of forming the same are provided. The methods may include forming a dummy channel region and an active region of a substrate, forming a bottom source/drain region on the active region, forming a gate electrode on one of opposing side surfaces of the dummy channel region, and forming first and second spacers on the opposing side surfaces of the dummy channel region, respectively. The gate electrode may include a first portion on the one of the opposing side surfaces of the dummy channel region and a second portion between the bottom source/drain region and the first spacer. The methods may also include forming a bottom source/drain contact by replacing the first portion of the gate electrode with a conductive material. The bottom source/drain contact may electrically connect the second portion of the gate electrode to the bottom source/drain region.

公开(公告)号：US11296210B2

公开(公告)日：2022-04-05

申请号：US16824196

申请日：2020-03-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seon-Bae Kim ,  Seung Hyun Song ,  Young Chai Jung

IPC: H01L29/66 ,  H01L21/308 ,  H01L29/06 ,  H01L21/033

Abstract: A method for manufacturing a fin structure of a vertical field effect transistor (VFET) includes: (a) patterning a lower layer and an upper layer, deposited on the lower layer, to form two patterns extended in two perpendicular directions, respectively; (b) forming a first spacer and a second spacer side by side in the two patterns along sidewalls of the lower layer and the upper layer exposed through the patterning; (c) removing the first spacer, the second spacer and the upper layer above a level of a top surface of the lower layer, and the first spacer below the level of the top surface of the lower layer and exposed through the two patterns in the plan view; (d) removing the lower layer, the upper layer, and the second spacer remaining on the substrate after operation (c); and (e) etching the substrate downward except a portion thereof below the first spacer remaining on the substrate after operation (d), and removing the remaining first spacer, thereby to obtain the fin structure.

公开(公告)号：US12142652B2

公开(公告)日：2024-11-12

申请号：US17491965

申请日：2021-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seon-Bae Kim ,  Kyungin Choi

IPC: H01L27/088 ,  H01L29/417 ,  H01L29/423

Abstract: A semiconductor device is disclosed. The semiconductor device may include a semiconductor substrate including a protruding active pattern, a first gate pattern provided on the active pattern and extended to cross the active pattern, a first capping pattern provided on a top surface of the first gate pattern, the first capping pattern having a top surface, a side surface, and a rounded edge, and a first insulating pattern covering the side surface and the edge of the first capping pattern. A thickness of the first insulating pattern on the edge of the first capping pattern is different from a thickness of the first insulating pattern on outer side surfaces of the spacer patterns.

公开(公告)号：US20240030345A1

公开(公告)日：2024-01-25

申请号：US18112312

申请日：2023-02-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Doohyun LEE ,  Heonjong Shin ,  Seon-Bae Kim ,  Jaeran Jang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08

CPC classification number: H01L29/78391 ,  H01L29/66545 ,  H01L29/0847 ,  H01L29/6656

Abstract: In some embodiments, the semiconductor device includes a substrate comprising a cell region, a dummy region spaced apart from the cell region in a first direction, and a border region between the cell region and the dummy region, an active pattern on the cell region, a device isolation layer on the substrate, source/drain patterns on the active pattern and channel patterns between the source/drain patterns, cell gate electrodes crossing the channel patterns in a second direction, active contacts disposed on the cell region and between the cell gate electrodes and coupled to the source/drain patterns, dummy gate electrodes on the dummy region and on the device isolation layer, dummy contacts on the dummy region and on a side surface of each of the dummy gate electrodes, an interlayer insulating layer on the side surface of each of the dummy gate electrodes, and a dam structure on the border region.

公开(公告)号：US20210111271A1

公开(公告)日：2021-04-15

申请号：US16824196

申请日：2020-03-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seon-Bae Kim ,  Seung Hyun Song ,  Young Chai Jung

IPC: H01L29/66 ,  H01L21/308 ,  H01L29/06

Abstract: A method for manufacturing a fin structure of a vertical field effect transistor (VFET) includes: (a) patterning a lower layer and an upper layer, deposited on the lower layer, to form two patterns extended in two perpendicular directions, respectively; (b) forming a first spacer and a second spacer side by side in the two patterns along sidewalls of the lower layer and the upper layer exposed through the patterning; (c) removing the first spacer, the second spacer and the upper layer above a level of a top surface of the lower layer, and the first spacer below the level of the top surface of the lower layer and exposed through the two patterns in the plan view; (d) removing the lower layer, the upper layer, and the second spacer remaining on the substrate after operation (c); and (e) etching the substrate downward except a portion thereof below the first spacer remaining on the substrate after operation (d), and removing the remaining first spacer, thereby to obtain the fin structure.

公开(公告)号：US20230402376A1

公开(公告)日：2023-12-14

申请号：US18095080

申请日：2023-01-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doohyun Lee ,  Heonjong Shin ,  Seon-Bae Kim

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/088 ,  H01L23/532 ,  H01L27/082

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L27/088 ,  H01L23/53295 ,  H01L27/082

Abstract: Semiconductor devices and fabrication methods thereof. For example, a semiconductor device may include a dielectric structure, and first conductive structures and second conductive structures. The dielectric structure may include a first dielectric layer that surrounds the first conductive structures and a second dielectric layer that surrounds the second conductive structures. The first dielectric layer may include a first intervention between the first conductive structures. The second dielectric layer may include a second intervention between the second conductive structures. A width in a first direction of the first intervention may decrease in a second direction from a top surface toward a bottom surface of the first intervention. A width in the first direction of the second intervention may increase in the second direction from a top surface toward a bottom surface of the second intervention. The first dielectric layer and the second dielectric layer may include different dielectric materials.

公开(公告)号：US20230207654A1

公开(公告)日：2023-06-29

申请号：US18054890

申请日：2022-11-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DOO HYUN LEE ,  Heon Jong Shin ,  Hyun Ho Park ,  Seon-Bae Kim ,  Jin Young Park ,  Jae Ran Jang

IPC: H01L29/45 ,  H01L29/06 ,  H01L29/08 ,  H01L29/161 ,  H01L29/423 ,  H01L29/417 ,  H01L29/775 ,  H01L21/285 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/45 ,  H01L21/28518 ,  H01L29/161 ,  H01L29/401 ,  H01L29/0673 ,  H01L29/775 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742

Abstract: A semiconductor device includes an active pattern that extends in a first direction; a plurality of gate structures that are spaced apart in the first direction, and include a gate electrode that extends in a second direction; a source/drain recess between adjacent gate structures; a source/drain pattern in the source/drain recess; a source/drain contact connected to the source/drain pattern and that includes a lower part on the source/drain pattern and an upper par; and a contact silicide film disposed along the lower part of the source/drain contact and between the source/drain contact and the source/drain region. The source/drain pattern includes a semiconductor liner film that extends along the source/drain recess and includes silicon germanium, a semiconductor filling film on the semiconductor liner film and that includes silicon germanium, and a semiconductor insertion film that extends along side walls of the lower part of the source/drain contact and includes silicon germanium.

公开(公告)号：US11552182B2

公开(公告)日：2023-01-10

申请号：US17399118

申请日：2021-08-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang Woo Sohn ,  Seung Hyun Song ,  Seon-Bae Kim ,  Min Cheol Oh ,  Young Chai Jung

IPC: H01L29/66

Abstract: Integrated circuit devices and methods of forming the same are provided. The methods may include forming a dummy channel region and an active region of a substrate, forming a bottom source/drain region on the active region, forming a gate electrode on one of opposing side surfaces of the dummy channel region, and forming first and second spacers on the opposing side surfaces of the dummy channel region, respectively. The gate electrode may include a first portion on the one of the opposing side surfaces of the dummy channel region and a second portion between the bottom source/drain region and the first spacer. The methods may also include forming a bottom source/drain contact by replacing the first portion of the gate electrode with a conductive material. The bottom source/drain contact may electrically connect the second portion of the gate electrode to the bottom source/drain region.

公开(公告)号：US20240413216A1

公开(公告)日：2024-12-12

申请号：US18808369

申请日：2024-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doohyun Lee ,  Heonjong Shin ,  Seon-Bae Kim ,  Minchan Gwak ,  Jinyoung Park ,  Hyunho Park

IPC: H01L29/417 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device may include an active pattern on a substrate, a source/drain pattern on the active pattern, a channel pattern connected to the source/drain pattern, a gate electrode on the channel pattern, an active contact on the source/drain pattern, a first lower interconnection line on the gate electrode, and a second lower interconnection line on the active contact and at the same level as the first lower interconnection line. The gate electrode may include an electrode body portion and an electrode protruding portion, wherein the electrode protruding portion protrudes from a top surface of the electrode body portion and is in contact with the first lower interconnection line thereon. The active contact may include a contact body portion and a contact protruding portion, wherein the contact protruding portion protrudes from a top surface of the contact body portion and is in contact with the second lower interconnection line thereon.

公开(公告)号：US12094940B2

公开(公告)日：2024-09-17

申请号：US17546213

申请日：2021-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doohyun Lee ,  Heonjong Shin ,  Seon-Bae Kim ,  Minchan Gwak ,  Jinyoung Park ,  Hyunho Park

IPC: H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/417 ,  H01L29/786 ,  H01L29/06

CPC classification number: H01L29/41775 ,  H01L27/092 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/0665

Abstract: A semiconductor device may include an active pattern on a substrate, a source/drain pattern on the active pattern, a channel pattern connected to the source/drain pattern, a gate electrode on the channel pattern, an active contact on the source/drain pattern, a first lower interconnection line on the gate electrode, and a second lower interconnection line on the active contact and at the same level as the first lower interconnection line. The gate electrode may include an electrode body portion and an electrode protruding portion, wherein the electrode protruding portion protrudes from a top surface of the electrode body portion and is in contact with the first lower interconnection line thereon. The active contact may include a contact body portion and a contact protruding portion, wherein the contact protruding portion protrudes from a top surface of the contact body portion and is in contact with the second lower interconnection line thereon.