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27 条记录 (耗时 0.019 秒)

    AUTOMATIC FREQUENCY CALIBRATION AND LOCK DETECTION CIRCUIT AND PHASE LOCKED LOOP INCLUDING THE SAME
    1.
    发明申请
    AUTOMATIC FREQUENCY CALIBRATION AND LOCK DETECTION CIRCUIT AND PHASE LOCKED LOOP INCLUDING THE SAME 有权

    公开(公告)号：US20220190834A1

    公开(公告)日：2022-06-16

    申请号：US17536514

    申请日：2021-11-29

    申请人： Samsung Electronics Co., Ltd.

    发明人： Baekmin LIM ,  Seungjin KIM

    IPC分类号： H03L7/095 ,  H03L7/089 ,  H03L7/099

    摘要： An automatic frequency calibration and lock detection circuit includes a frequency error generator circuit, an automatic frequency calibration signal generator circuit, and a lock flag generator circuit. The frequency error generator circuit generates a frequency error signal based on a reference frequency signal and an output frequency signal. The frequency error signal represents a difference between a frequency of the output frequency signal and a target frequency. The automatic frequency calibration signal generator circuit generates an automatic frequency calibration output signal and an automatic frequency calibration done signal based on the frequency error signal and a first clock signal. The lock flag generator circuit generates a lock done signal based on the frequency error signal, the automatic frequency calibration done signal and a second clock signal. The frequency error generator circuit is shared by the automatic frequency calibration signal generator circuit and the lock flag generator circuit.

    FRACTIONAL DIVIDER WITH PHASE SHIFTER AND FRACTIONAL PHASE LOCKED LOOP INCLUDING THE SAME
    4.
    发明公开
    FRACTIONAL DIVIDER WITH PHASE SHIFTER AND FRACTIONAL PHASE LOCKED LOOP INCLUDING THE SAME 审中-公开

    公开(公告)号：US20230170912A1

    公开(公告)日：2023-06-01

    申请号：US17964377

    申请日：2022-10-12

    申请人： Samsung Electronics Co., Ltd.

    发明人： Baekmin LIM ,  Seungjin KIM ,  Seunghyun OH

    IPC分类号： H03L7/197 ,  H03L7/081 ,  H03L7/093

    CPC分类号： H03L7/1976 ,  H03L7/081 ,  H03L7/093

    摘要： A fractional divider processing circuitry is to receive one of a plurality of clock signals as an input clock signal, and generate a first division clock signal based on the input clock signal and a first control signal. Phases of the plurality of clock signals partially overlap each other. The processing circuitry generates a delta-sigma modulation signal based on the first division clock signal and a frequency control word, and generates a second division clock signal based on the plurality of clock signals, the first division clock signal and a second control signal. The second control signal corresponds to a quantization noise of the delta-sigma modulation signal. The processing circuitry generates the second control signal and a digital control word based on the quantization noise of the delta-sigma modulator. The processing circuitry generates a final division clock signal based on the second division clock signal and the digital control word.

    SUB-SAMPLING PHASE LOCKED LOOP WITH COMPENSATED LOOP BANDWIDTH AND INTEGRATED CIRCUIT INCLUDING THE SAME
    5.
    发明申请
    SUB-SAMPLING PHASE LOCKED LOOP WITH COMPENSATED LOOP BANDWIDTH AND INTEGRATED CIRCUIT INCLUDING THE SAME 有权

    公开(公告)号：US20230122691A1

    公开(公告)日：2023-04-20

    申请号：US17865811

    申请日：2022-07-15

    申请人： Samsung Electronics Co., Ltd.

    发明人： Gyusik KIM ,  Seungjin KIM ,  Seunghyun OH

    IPC分类号： H03L7/091 ,  H03L7/099

    摘要： A sub-sampling phase locked loop includes a slope generating and sampling circuit, first and second transconductance circuits, a constant transconductance bias circuit, a loop filter and a voltage controlled oscillator. The slope generating and sampling circuit generates a sampling voltage based on a reference clock signal and an output clock signal. The first and second transconductance circuits generate first and second output control voltages based on the sampling voltage, a reference voltage and a control current. The constant transconductance bias circuit includes a switched capacitor resistor. The constant transconductance bias circuit is configured to generate the control current. The loop filter is connected to output terminals of the first and second transconductance circuits. The voltage controlled oscillator generates the output clock signal based on the first and second output control voltages.

    ELECTRONIC DEVICE COMPRISING DISPLAY, AND OPERATION METHOD THEREOF
    7.
    发明公开
    ELECTRONIC DEVICE COMPRISING DISPLAY, AND OPERATION METHOD THEREOF 审中-公开

    公开(公告)号：US20230178050A1

    公开(公告)日：2023-06-08

    申请号：US18104965

    申请日：2023-02-02

    申请人： SAMSUNG ELECTRONICS CO, LTD.

    发明人： Gwanghui LEE ,  Minwoo LEE ,  Minwoo KIM ,  Seungjin KIM ,  Woojun JUNG

    IPC分类号： G09G5/12

    CPC分类号： G09G5/12 ,  G09G2320/0626 ,  G09G2340/0435

    摘要： On an electronic device which includes a display device comprising a display driving circuit, a processor, and a memory a method for changing a refresh rate of the display device includes: changing at least one of a first parameter, a second parameter, or a third parameter in response to identifying the occurrence of at least one of a scan rate change request or a change in scan rate change restriction, and applying the changed parameter among the first parameter, the second parameter, and the third parameter. The first parameter is the frequency of a first synchronization signal generated in the display driving circuit, the second parameter is the increase or decrease in a blank area to substitute for a portion of active video area in frame information, and the third parameter is the frequency of a second synchronization signal for rendering.

    ELECTRONIC DEVICE COMPRISING DISPLAY AND OPERATION METHOD THEREOF
    8.
    发明公开
    ELECTRONIC DEVICE COMPRISING DISPLAY AND OPERATION METHOD THEREOF 审中-公开

    公开(公告)号：US20230154431A1

    公开(公告)日：2023-05-18

    申请号：US18100069

    申请日：2023-01-23

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Gwanghui LEE ,  Minwoo LEE ,  Seungjin KIM ,  Woojun JUNG ,  Kwonsoo KIM ,  Kimyung LEE ,  Minwoo KIM

    IPC分类号： G09G5/00 ,  G06F3/041

    CPC分类号： G09G5/001 ,  G09G5/003 ,  G06F3/0416 ,  G09G2310/0245

    摘要： An electronic device includes a display including a plurality of pixels; a display driver configured to provide a data voltage to the plurality of pixels of the display; and a processor configured to: obtain frequency change-based event information, determine a first frequency and a second frequency higher than the first frequency based on the frequency change-based event information, the first frequency being a target value of a refresh frequency, and provide frame data to the display driver, wherein the processor is further configured to control the display driver to: set a frame section in which the display is driven, during a first frame, generate the data voltage based on the frame data and provide the data voltage to the plurality of pixels, and during a low-frequency driving section, in which the frame data is not obtained, after the first frame, refresh an image based on the second frequency and refresh the image based on the first frequency.

    ELECTRONIC DEVICE AND METHOD FOR CONTROLLING TIMING SIGNAL
    10.
    发明申请
    ELECTRONIC DEVICE AND METHOD FOR CONTROLLING TIMING SIGNAL 有权

    公开(公告)号：US20210248980A1

    公开(公告)日：2021-08-12

    申请号：US17155132

    申请日：2021-01-22

    申请人： Samsung Electronics Co., Ltd.

    发明人： Gwanghui LEE ,  Minwoo KIM ,  Seungjin KIM ,  Minwoo LEE ,  Juseok LEE ,  Woojun JUNG

    IPC分类号： G09G5/36 ,  G09G5/18 ,  G09G5/12

    摘要： According to an embodiment, an electronic device may include at least one processor, a display, a memory configured to store image frames, and a display controller configured to output the image frames. The at least one processor may be configured to transmit a first image frame to be output through the display, based on a first timing signal received from the display controller, identify a state of the electronic device, transmit first control information for changing a timing of the first timing signal, in response to transmitting the first control information for changing the timing of the first timing signal, receive a second timing signal from the display controller, and transmit, to the memory, a second image frame to be output through the display, based on the received second timing signal. The timing of the second timing signal may differ from the timing of the first timing signal.