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公开(公告)号：US12113887B2
公开(公告)日：2024-10-08
申请号：US17881417
申请日：2022-08-04
发明人： Seon-Ho Han , Young-Su Kwon
CPC分类号： H04L7/033 , H03L7/0807 , H03L7/093
摘要： Disclosed are a digital CDR circuit and a feedback loop circuit including the same. The digital CDR circuit includes a phase detector that receives an input signal and outputs a phase detection result signal corresponding to a determination result for a sampling time based on the input signal, a charge pump that receives the phase detection result signal and outputs an amplified signal obtained by multiplying the phase detection result signal by a gain, a loop filter that receives the amplified signal and filters the amplified signal to output a filtered signal, and a phase shift control code generator that generates a control signal for controlling a phase of a signal based on the filtered signal, and the input signal includes plural data signals and plural error signals, and the data signals and the error signals are digital signals which are quantized based on a signal magnitude.
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2.发明公开公开(公告)号：US20240291495A1
公开(公告)日：2024-08-29
申请号：US18114847
申请日：2023-02-27
发明人： Ping LU , Bupesh PANDITA , Minhan CHEN
CPC分类号： H03L7/107 , G04F10/005 , H03L7/085 , H03L7/093 , H03L7/099 , H03L7/1077
摘要： In a calibrated phase-locked loop (PLL), a time-to-digital (TDC) converter circuit can be calibrated to a nominal gain by a calibration circuit to achieve a desired jitter response in the PLL. The TDC circuit in the PLL measures a time difference between the reference clock and a feedback signal as a number of time increments, and the calibration circuit adjusts a resolution of the measurement by adjusting the length of the time increments (i.e., resolution). In a Vernier method employed to measure the time difference, the length of a time increment is determined by a delay difference between a first delay of a first delay circuit in a first series of first delay circuits and a second delay of a second delay circuit in a second series of second delay circuits. Adjusting the resolution of the TDC circuit includes adjusting the delay difference between the first delay and the second delay.
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公开(公告)号：US12052023B1
公开(公告)日：2024-07-30
申请号：US18158662
申请日：2023-01-24
CPC分类号： H03L7/187 , H03L7/093 , H03L7/0992
摘要： A clock recovery circuit includes a frequency tracking loop including a first charge pump, and a phase tracking loop including a second charge pump. A voltage-controlled oscillator responds to the frequency tracking loop in a first operating mode and to the phase tracking loop in a second operating mode. A lock detector outputs an activation signal that indicates whether the clock recovery circuit has acquired frequency lock. A loop filter coupled to an input of the voltage-controlled oscillator includes a switchable resistor and a programmable delay element responsive to the activation signal. The first charge pump is disabled when the activation signal indicates frequency lock has been acquired, and disabled when the activation signal indicates frequency lock has not been acquired. The switchable resistor is bypassed when an output of the programmable delay element is in the first signaling state.
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公开(公告)号：US12046271B2
公开(公告)日：2024-07-23
申请号：US18509485
申请日：2023-11-15
发明人： Jingwei Cheng
CPC分类号： G11C11/4076 , G11C7/1093 , G11C7/222 , G11C29/023 , H03L7/093 , H03L7/0992
摘要： A clock system and a memory are disclosed. The clock system includes a system on chip (SoC) configured to generate a first oscillation signal, a second oscillation signal, a third oscillation signal and a fourth oscillation signal of a same frequency and amplitude. Further, the clock system includes a memory chip configured to output a data signal based on signal edges of the first oscillation signal, the second oscillation signal, the third oscillation signal and the fourth oscillation signal, and output a command/address signal based on the signal edges of the first oscillation signal and the third oscillation signal. The signal edges are rising edges or falling edges.
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公开(公告)号：US20240195423A1
公开(公告)日：2024-06-13
申请号：US18510215
申请日：2023-11-15
IPC分类号： H03L7/093 , G01R29/26 , G01R31/317 , G04F10/00
CPC分类号： H03L7/093 , G01R29/26 , G01R31/31727 , G04F10/005
摘要： A spur measurement system uses a first device with a spur cancellation circuit that cancel spurs responsive to a frequency control word identifying a spurious tone of interest. A device under test generates a clock signal and supplies the clock signal to the first device through an optional divider. The spur cancellation circuit in the first device generates sine and cosine weights at the spurious tone of interest as part of the spur cancellation process. A first magnitude of the spurious tone in a phase-locked loop in the first device is determined according to the sine and cosine weights and a second magnitude of the spurious tone in the clock signal is determined by the first magnitude divided by gains associated with the first device.
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公开(公告)号：US12009826B1
公开(公告)日：2024-06-11
申请号：US17983253
申请日：2022-11-08
申请人： Anritsu Company
摘要： Circuits, methods, and apparatus that can reduce or suppress phase noise in a frequency synthesizer. A phase-noise-suppression system can detect phase noise in an input signal, amplify the detected phase noise, subtract the detected phase noise from the input signal, and provide an output signal having reduced phase noise.
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公开(公告)号：US20240187004A1
公开(公告)日：2024-06-06
申请号：US18287746
申请日：2022-04-26
发明人： Brent CARLSON
摘要： A digital clean-up oscillator and associated method are provided for cleaning jitter from a noisy clock signal, comprising receiving a reference clock oscillator signal and the noisy clock signal to be cleaned: measuring the frequency of the reference clock signal in the time domain of the noisy clock signal: filtering any frequency variations from the measured frequency of the reference clock signal on timescales shorter than a phase change interval Tau_clean over which jitter in the noisy clock signal is to be cleaned; generating a phase increment signal DDS_pinc based on the measured and filtered frequency of the reference clock signal: clocking the phase increment signal DDS_pinc with the reference clock signal for generating an output digital phase ramp signal φ_DDS(t) that tracks the frequency of the noisy clock signal with phase wander removed on timescales less than the phase change interval Tau_clean; and converting the output digital phase ramp signal φ_DDS(t) to an output jitter-cleaned time domain clock signal frequency locked to the noisy clock signal.
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8.发明公开公开(公告)号：US20240162906A1
公开(公告)日：2024-05-16
申请号：US18488785
申请日：2023-10-17
申请人： MediaTek Inc.
发明人： Ahmed Safwat Mohamed Aboelenein Elmallah , Mohammed Mohsen Abdulsalam Abdullatif , Tamer Mohammed Ali
IPC分类号： H03L7/093
CPC分类号： H03L7/093
摘要： The techniques described herein relate to systems, apparatus, articles of manufacture, and methods for optimum loop gain calibration for clock data recovery and phase locked loop. An example apparatus includes a phase detector with a phase detector output and configured to generate an error signal representative of a difference between an input signal and a feedback signal. The apparatus further includes a calibrator circuit with a calibrator input coupled to the phase detector output and configured to determine correlation value associated with the error signal, and determine a gain value based on an adjustment of an absolute value of the correlation value by a pseudorandom binary sequence signal.
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公开(公告)号：US11962315B2
公开(公告)日：2024-04-16
申请号：US17916200
申请日：2020-03-31
CPC分类号： H03L7/0992 , H03B5/1212 , H03L7/093 , H03B2201/0208
摘要： A phase-locked loop comprises a voltage controlled oscillator. The voltage controlled oscillator comprises an inductor and a capacitor, connected in parallel, and also connected in parallel therewith, a negative resistance structure. A first terminal of the negative resistance structure is connected to respective first terminals of the inductor and the capacitor. A second terminal of the negative resistance structure is connected to respective second terminals of the inductor and the capacitor. The negative resistance structure exhibits a tunable capacitance, such that a frequency of an output of the voltage controlled oscillator can be tuned by a control input signal, and the control input signal is generated in the phase-locked loop. The negative resistance structure comprises first and second transistors. There is a first conduction path between the first terminal of the first transistor and the control terminal of the second transistor, and a second conduction path between the control terminal of the first transistor and the first terminal of the second transistor. The control terminal of at least one of the first and second transistors is biased by the control input signal, such that a parasitic capacitance of said at least one of the first and second transistors can be tuned by the control input signal, in order to tune the frequency of the output of the voltage controlled oscillator, and hence the frequency of oscillation of the phase-locked loop.
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公开(公告)号：US11909405B1
公开(公告)日：2024-02-20
申请号：US18151861
申请日：2023-01-09
发明人： Luigi Grimaldi , Thomas Bauernfeind , Dmytro Cherniak , Fabio Versolatto , Andrew Wightwick , Fabio Padovan , Giovanni Boi
摘要： A digital phase-locked loop (DPLL) circuit includes: a first time-to-digital converter (TDC) and a first digital loop filter (DLF) that are configured to be coupled between a reference clock source and a digitally controlled oscillator (DCO), where the first TDC is configured to, during an acquisition mode, generate a phase error by: receiving a reference clock signal from the reference clock source; receiving a clock signal that is based on an output of the DCO divided by a dividing factor, computing a phase error using the reference clock signal and the clock signal; detecting cycle slipping in the computed phase error; and in response to detecting the cycle slipping, modifying the computed phase error to reduce the impact of cycle slipping on the DPLL circuit; and a first frequency divider circuit configured to generate the clock signal by dividing the output of the DCO by the dividing factor.
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