公开(公告)号：US20250071991A1

公开(公告)日：2025-02-27

申请号：US18583121

申请日：2024-02-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangwoo HAN ,  Jongho WOO ,  Seung Min LEE ,  Moonkang CHOI

IPC: H10B43/27 ,  H01L25/065 ,  H10B43/10 ,  H10B43/35 ,  H10B51/10 ,  H10B51/20 ,  H10B80/00

Abstract: A semiconductor device includes a source structure comprising a first source layer, a second source layer on the first source layer, and a third source layer on the second source layer, a gate stack structure on the source structure, the gate stack structure with alternating insulating patterns and conductive patterns, and a memory channel structure penetrating the gate stack structure. The memory channel structure includes a channel layer and a memory layer surrounding the channel layer. The channel layer penetrates the memory layer and the second source layer, and a bottom surface of the channel layer is in contact with the source structure.

公开(公告)号：US20250063731A1

公开(公告)日：2025-02-20

申请号：US18650189

申请日：2024-04-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangwoo HAN ,  Jongho WOO ,  Seung Min LEE ,  Moonkang CHOI

IPC: H10B43/27 ,  H01L25/065 ,  H10B43/10 ,  H10B43/35 ,  H10B51/10 ,  H10B51/20 ,  H10B80/00

Abstract: A semiconductor device includes a source structure having a first source layer, a second source layer on the first source layer, and a third source layer on the second source layer. A gate stack structure is on the source structure. The gate stack structure includes dielectric patterns and conductive patterns that are alternately stacked. A memory channel structure penetrates the gate stack structure. The memory channel structure includes a channel layer. A data storage layer surrounds the channel layer. A blocking layer surrounds the data storage layer. The second source layer includes an inner sidewall directly contacting the channel layer. The third source layer includes an inner sidewall directly contacting the data storage layer.

公开(公告)号：US20240276733A1

公开(公告)日：2024-08-15

申请号：US18405361

申请日：2024-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyuncheol KIM ,  Yongseok KIM ,  Sanghyun PARK ,  Kiheun LEE ,  Sangwoo HAN

IPC: H10B51/30 ,  H10B51/20

CPC classification number: H10B51/30 ,  H10B51/20

Abstract: A semiconductor memory device includes a substrate, a semiconductor pattern on the substrate and including a source region having a first conductivity type, a drain region having a second conductivity type, and an intrinsic region between the source region and the drain region, first and second gate electrodes on the intrinsic region, a ferroelectric pattern between the intrinsic region and the first and second gate electrodes, and a gate dielectric pattern between the ferroelectric pattern and the intrinsic region.