公开(公告)号：US20230180481A1

公开(公告)日：2023-06-08

申请号：US18062245

申请日：2022-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hagyoul Bae ,  Seungyeul Yang ,  Minhyun Lee ,  Jinseong Heo ,  Taehwan Moon

IPC: H10B51/20 ,  H10B51/30

CPC classification number: H01L27/11597 ,  H01L27/1159

Abstract: A vertical non-volatile memory device may include a plurality of insulating layers and a plurality of conductive layers alternately stacked on a surface of a substrate in a direction perpendicular to the surface of the substrate; a channel layer on the substrate, where the channel layer extends in the direction perpendicular to the surface of the substrate and the channel layer may be on lateral surfaces of the plurality of insulating layers and lateral surfaces of the plurality of conductive layers; and a ferroelectric layer between the channel layer and the lateral surfaces of the plurality of conductive layers.

公开(公告)号：US20240221832A1

公开(公告)日：2024-07-04

申请号：US18328192

申请日：2023-06-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seyun KIM ,  Kyunghun Kim ,  Sunho Kim ,  Hyungyung Kim ,  Seungyeul Yang ,  Gukhyon Yon ,  Minhyun Lee ,  Joonsuk Lee ,  Seokhoon Choi ,  Hoseok Heo

IPC: G11C16/04 ,  H01L29/16 ,  H01L29/18 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C16/0483 ,  H01L29/1606 ,  H01L29/18 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: Provided is a nonvolatile memory device. The nonvolatile memory device includes: a channel layer; a plurality of gate electrodes and a plurality of insulating layers being spaced apart from the channel layer and being alternately arranged; a charge trap layer between the channel layer and a gate electrode, and a charge tunneling layer between the channel layer and the charge trap layer.

公开(公告)号：US20240215250A1

公开(公告)日：2024-06-27

申请号：US18340419

申请日：2023-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seyun KIM ,  Jooheon Kang ,  Yumin Kim ,  Garam Park ,  Hyunjae Song ,  Dongho Ahn ,  Seungyeul Yang ,  Myunghun Woo ,  Jinwoo Lee ,  Seungdam Hyun

IPC: H10B43/35 ,  G11C16/04 ,  H10B43/10 ,  H10B43/27

CPC classification number: H10B43/35 ,  G11C16/0483 ,  H10B43/10 ,  H10B43/27

Abstract: A memory device including the vertical stack structure includes a gate electrode, a resistance change layer, a channel between the gate electrode and the resistance change layer, and an island structure between the resistance change layer and the channel and in contact with the resistance change layer and the channel, and a gate insulating layer between the gate electrode and the channel.

公开(公告)号：US20240065000A1

公开(公告)日：2024-02-22

申请号：US18169436

申请日：2023-02-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yumin Kim ,  Jooheon Kang ,  Sunho Kim ,  Seyun Kim ,  Garam Park ,  Hyunjae Song ,  Dongho Ahn ,  Seungyeul Yang ,  Myunghun Woo ,  Jinwoo Lee

IPC: H10B63/00 ,  G11C13/00 ,  G06N3/063

CPC classification number: H10B63/34 ,  G11C13/0007 ,  G11C13/003 ,  H10B63/845 ,  G06N3/063 ,  G11C2213/71 ,  G11C2213/75 ,  G11C2213/79

Abstract: Provided are a nonvolatile memory device and an operating method thereof. The nonvolatile memory device may include a conductive pillar, a resistance change layer surrounding a side surface of the conductive pillar, a semiconductor layer surrounding a side surface of the resistance change layer, a gate insulating layer surrounding a side surface of the semiconductor layer, and a plurality of insulating patterns and a plurality of gate electrodes alternately arranged along a surface of the gate insulating layer. The plurality of insulating patterns and the plurality of gate electrodes may surround a side surface of the gate insulating layer.