公开(公告)号：US20250017017A1

公开(公告)日：2025-01-09

申请号：US18439308

申请日：2024-02-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hoseok Heo ,  Kyunghun Kim ,  Sunho Kim ,  Hyungyung Kim ,  Minhyun Lee ,  Seokhoon Choi ,  Seungdam Hyun

IPC: H10B43/35 ,  H01L29/423

Abstract: A vertical NAND flash memory device and an electronic apparatus including the same are provided. The vertical NAND flash memory device includes a plurality of cell arrays. Each of the plurality of cell arrays includes a channel layer, a charge trap layer, and a plurality of gate electrodes provided on the charge trap layer. The charge trap layer includes a matrix including amorphous metal oxynitride and nanocrystals dispersed in the matrix and including nitride having semiconductor characteristics.

公开(公告)号：US20240221832A1

公开(公告)日：2024-07-04

申请号：US18328192

申请日：2023-06-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seyun KIM ,  Kyunghun Kim ,  Sunho Kim ,  Hyungyung Kim ,  Seungyeul Yang ,  Gukhyon Yon ,  Minhyun Lee ,  Joonsuk Lee ,  Seokhoon Choi ,  Hoseok Heo

IPC: G11C16/04 ,  H01L29/16 ,  H01L29/18 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C16/0483 ,  H01L29/1606 ,  H01L29/18 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: Provided is a nonvolatile memory device. The nonvolatile memory device includes: a channel layer; a plurality of gate electrodes and a plurality of insulating layers being spaced apart from the channel layer and being alternately arranged; a charge trap layer between the channel layer and a gate electrode, and a charge tunneling layer between the channel layer and the charge trap layer.