A vertical memory device may include a cell stacked structure on a substrate, wherein the cell stacked structure includes an insulation layer pattern and a gate pattern are alternately and repeatedly stacked, and wherein the cell stacked structure extends in a first direction parallel to an upper surface of the substrate, and wherein an edge portion in the first direction of the cell stacked region is disposed in the second region and has a step portion having a step shape; an etch stop structure on an upper surface of each of gate patterns of the step portion of the cell stacked structure, wherein the etch stop structure includes a transition metal oxide; an insulating interlayer covering the cell stacked structure; and a contact plug passing through the insulating interlayer and the etch stop structure, wherein the contact plug contacts the upper surface of each of the gate patterns.