公开(公告)号：US20230163030A1

公开(公告)日：2023-05-25

申请号：US18151378

申请日：2023-01-06

Applicant: Micron Technology, Inc.

Inventor： Trupti D. Gawai ,  David A. Kewley ,  Aaron M. Lowe ,  Radhakrishna Kotti ,  David S. Pratt

IPC: H01L21/768 ,  H01L23/535

CPC classification number: H01L21/76895 ,  H01L21/76805 ,  H01L23/535

Abstract: Methods of manufacturing semiconductor devices, and associated systems and devices, are disclosed herein. In some embodiments, a method of manufacturing a semiconductor device includes forming an opening in an insulative material at least partially over an electrically conductive feature. The method can further include forming a ring of electrically non-conductive material extending at least partially about a sidewall of the insulative material that defines the opening. The method can further include removing a portion of the ring to form an opening over the electrically conductive feature, and then depositing an electrically conductive material into the opening in the ring to form a conductive via electrically coupled to the electrically conductive feature.

公开(公告)号：US11636911B2

公开(公告)日：2023-04-25

申请号：US17387290

申请日：2021-07-28

Applicant: Micron Technology, Inc.

Inventor： Amitava Majumdar ,  Radhakrishna Kotti ,  Patrick Daniel White ,  Pavan Reddy K Aella ,  Rajesh Kamana

IPC: G11C29/38 ,  G11C5/06 ,  G11C29/44 ,  H01L21/66 ,  H04B17/354 ,  H04B1/525 ,  G06F3/06

Abstract: Methods, systems, and devices for leakage source detection are described. In some cases, a testing device may scan a first set of access lines of a memory die that have a first length and a second set of access lines of the memory die that have a second length different than the first length. The testing device may determine a first error rate associated with the first set of access lines and a second error rate associated with the second set of access lines. The testing device may categorize a performance of the memory die based on the first and second error rates. In some cases, the testing device may determine a third error rate associated with a type of error based on the first and second error rates and may categorize the performance of the memory die based on the third error rate.

公开(公告)号：US11574842B2

公开(公告)日：2023-02-07

申请号：US17230833

申请日：2021-04-14

Applicant: Micron Technology, Inc.

Inventor： Trupti D. Gawai ,  David A. Kewley ,  Aaron M. Lowe ,  Radhakrishna Kotti ,  David S. Pratt

IPC: H01L21/768 ,  H01L23/535

Abstract: Methods of manufacturing semiconductor devices, and associated systems and devices, are disclosed herein. In some embodiments, a method of manufacturing a semiconductor device includes forming an opening in an insulative material at least partially over an electrically conductive feature. The method can further include forming a ring of electrically non-conductive material extending at least partially about a sidewall of the insulative material that defines the opening. The method can further include removing a portion of the ring to form an opening over the electrically conductive feature, and then depositing an electrically conductive material into the opening in the ring to form a conductive via electrically coupled to the electrically conductive feature.

公开(公告)号：US11961556B2

公开(公告)日：2024-04-16

申请号：US17568461

申请日：2022-01-04

Applicant: Micron Technology, Inc.

Inventor： Amitava Majumdar ,  Radhakrishna Kotti ,  Rajasekhar Venigalla

IPC: G11C5/06 ,  G11C13/00 ,  H01L23/522 ,  H01L23/528 ,  H10B63/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: G11C13/0028 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/004 ,  G11C13/0069 ,  H01L23/5226 ,  H01L23/528 ,  H10B63/84 ,  H10N70/231 ,  H10N70/826 ,  G11C2213/52 ,  G11C2213/71 ,  H10N70/841 ,  H10N70/8825

Abstract: Methods, systems, and devices supporting a socket design for a memory device are described. A die may include one or more memory arrays, which each may include any number of word lines and any number of bit lines. The word lines and the bit lines may be oriented in different directions, and memory cells may be located at the intersections of word lines and bit lines. Sockets may couple the word lines and bit lines to associated drivers, and the sockets may be located such that memory cells farther from a corresponding word line socket are nearer a corresponding bit line socket, and vice versa. For example, sockets may be disposed in rows or regions that are parallel to one another, and which may be non-orthogonal to the corresponding word lines and bit lines.

公开(公告)号：US20230021072A1

公开(公告)日：2023-01-19

申请号：US17947038

申请日：2022-09-16

Applicant: Micron Technology, Inc.

Inventor： Raju Ahmed ,  Radhakrishna Kotti ,  David A. Kewley ,  Dave Pratt

IPC: H01L23/528 ,  H01L23/522

Abstract: Some embodiments include an integrated assembly having a base which includes first circuitry. Memory decks are over the base. Each of the memory decks has a sense/access line coupled with the first circuitry. The memory decks and base are vertically spaced from one another by gaps. The gaps alternate in a vertical direction between first gaps and second gaps. Overlapping conductive paths extend from the sense/access lines to the first circuitry. The conductive paths include first conductive interconnects within the first gaps and second conductive interconnects within the second gaps. The first and second conductive interconnects are laterally offset relative to one another.

公开(公告)号：US20220208264A1

公开(公告)日：2022-06-30

申请号：US17568461

申请日：2022-01-04

Applicant: Micron Technology, Inc.

Inventor： Amitava Majumdar ,  Radhakrishna Kotti ,  Rajasekhar Venigalla

IPC: G11C13/00 ,  H01L23/528 ,  H01L23/522 ,  H01L27/24 ,  H01L45/00

Abstract: Methods, systems, and devices supporting a socket design for a memory device are described. A die may include one or more memory arrays, which each may include any number of word lines and any number of bit lines. The word lines and the bit lines may be oriented in different directions, and memory cells may be located at the intersections of word lines and bit lines. Sockets may couple the word lines and bit lines to associated drivers, and the sockets may be located such that memory cells farther from a corresponding word line socket are nearer a corresponding bit line socket, and vice versa. For example, sockets may be disposed in rows or regions that are parallel to one another, and which may be non-orthogonal to the corresponding word lines and bit lines.

公开(公告)号：US20220013449A1

公开(公告)日：2022-01-13

申请号：US16925767

申请日：2020-07-10

Applicant: Micron Technology, Inc.

Inventor： Raju Ahmed ,  Radhakrishna Kotti ,  David A. Kewley ,  Dave Pratt

IPC: H01L23/528 ,  H01L23/522

Abstract: Some embodiments include an integrated assembly having a base which includes first circuitry. Memory decks are over the base. Each of the memory decks has a sense/access line coupled with the first circuitry. The memory decks and base are vertically spaced from one another by gaps. The gaps alternate in a vertical direction between first gaps and second gaps. Overlapping conductive paths extend from the sense/access lines to the first circuitry. The conductive paths include first conductive interconnects within the first gaps and second conductive interconnects within the second gaps. The first and second conductive interconnects are laterally offset relative to one another.

公开(公告)号：US20210151119A1

公开(公告)日：2021-05-20

申请号：US16684533

申请日：2019-11-14

Applicant: Micron Technology, Inc.

Inventor： Amitava Majumdar ,  Radhakrishna Kotti ,  Patrick Daniel White ,  Pavan Reddy K. Aella ,  Rajesh Kamana

IPC: G11C29/38 ,  H01L21/66 ,  G11C29/44

Abstract: Methods, systems, and devices for leakage source detection are described. In some cases, a testing device may scan a first set of access lines of a memory die that have a first length and a second set of access lines of the memory die that have a second length different than the first length. The testing device may determine a first error rate associated with the first set of access lines and a second error rate associated with the second set of access lines. The testing device may categorize a performance of the memory die based on the first and second error rates. In some cases, the testing device may determine a third error rate associated with a type of error based on the first and second error rates and may categorize the performance of the memory die based on the third error rate.

公开(公告)号：US20240347107A1

公开(公告)日：2024-10-17

申请号：US18616989

申请日：2024-03-26

Applicant: Micron Technology, Inc.

Inventor： Amitava Majumdar ,  Radhakrishna Kotti ,  Rajasekhar Venigalla

IPC: G11C13/00 ,  H01L23/522 ,  H01L23/528 ,  H10B63/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: G11C13/0028 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/004 ,  G11C13/0069 ,  H01L23/5226 ,  H01L23/528 ,  H10B63/84 ,  H10N70/231 ,  H10N70/826 ,  G11C2213/52 ,  G11C2213/71 ,  H10N70/841 ,  H10N70/8825

Abstract: Methods, systems, and devices supporting a socket design for a memory device are described. A die may include one or more memory arrays, which each may include any number of word lines and any number of bit lines. The word lines and the bit lines may be oriented in different directions, and memory cells may be located at the intersections of word lines and bit lines. Sockets may couple the word lines and bit lines to associated drivers, and the sockets may be located such that memory cells farther from a corresponding word line socket are nearer a corresponding bit line socket, and vice versa. For example, sockets may be disposed in rows or regions that are parallel to one another, and which may be non-orthogonal to the corresponding word lines and bit lines.

公开(公告)号：US12014983B2

公开(公告)日：2024-06-18

申请号：US17947038

申请日：2022-09-16

Applicant: Micron Technology, Inc.

Inventor： Raju Ahmed ,  Radhakrishna Kotti ,  David A. Kewley ,  Dave Pratt

IPC: H01L23/528 ,  H01L23/522 ,  H10B61/00 ,  H10B63/00

CPC classification number: H01L23/528 ,  H01L23/5226 ,  H10B61/00 ,  H10B63/84

Abstract: Some embodiments include an integrated assembly having a base which includes first circuitry. Memory decks are over the base. Each of the memory decks has a sense/access line coupled with the first circuitry. The memory decks and base are vertically spaced from one another by gaps. The gaps alternate in a vertical direction between first gaps and second gaps. Overlapping conductive paths extend from the sense/access lines to the first circuitry. The conductive paths include first conductive interconnects within the first gaps and second conductive interconnects within the second gaps. The first and second conductive interconnects are laterally offset relative to one another.