公开(公告)号：US12014983B2

公开(公告)日：2024-06-18

申请号：US17947038

申请日：2022-09-16

Applicant: Micron Technology, Inc.

Inventor： Raju Ahmed ,  Radhakrishna Kotti ,  David A. Kewley ,  Dave Pratt

IPC: H01L23/528 ,  H01L23/522 ,  H10B61/00 ,  H10B63/00

CPC classification number: H01L23/528 ,  H01L23/5226 ,  H10B61/00 ,  H10B63/84

Abstract: Some embodiments include an integrated assembly having a base which includes first circuitry. Memory decks are over the base. Each of the memory decks has a sense/access line coupled with the first circuitry. The memory decks and base are vertically spaced from one another by gaps. The gaps alternate in a vertical direction between first gaps and second gaps. Overlapping conductive paths extend from the sense/access lines to the first circuitry. The conductive paths include first conductive interconnects within the first gaps and second conductive interconnects within the second gaps. The first and second conductive interconnects are laterally offset relative to one another.

公开(公告)号：US20230113573A1

公开(公告)日：2023-04-13

申请号：US18048633

申请日：2022-10-21

Applicant: Micron Technology, Inc.

Inventor： Trupti D. Gawai ,  David S. Pratt ,  Ahmed M. Elsied ,  David A. Kewley ,  Dale W. Collins ,  Raju Ahmed ,  Chelsea M. Jordan ,  Radhakrishna Kotti

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: Methods of manufacturing semiconductor devices, and associated systems and devices, are disclosed herein. In some embodiments, a method of manufacturing a semiconductor device includes forming an opening in an electrically insulative material at least partially over a first electrically conductive feature and a second electrically conductive feature. The method can further include forming a ring of electrically conductive material around a sidewall of the insulative material defining the opening, wherein the ring of electrically conductive material includes (a) a first via portion over the first electrically conductive feature, (b) a second via portion over the second electrically conductive feature, and (c) connecting portions extending between the first and second via portions. Finally, the method can include removing the connecting portions of the ring of electrically conductive material to electrically isolate the first via portion from the second via portion.

公开(公告)号：US11482492B2

公开(公告)日：2022-10-25

申请号：US16925767

申请日：2020-07-10

Applicant: Micron Technology, Inc.

Inventor： Raju Ahmed ,  Radhakrishna Kotti ,  David A. Kewley ,  Dave Pratt

IPC: H01L27/22 ,  H01L27/24 ,  H01L23/528 ,  H01L23/522

Abstract: Some embodiments include an integrated assembly having a base which includes first circuitry. Memory decks are over the base. Each of the memory decks has a sense/access line coupled with the first circuitry. The memory decks and base are vertically spaced from one another by gaps. The gaps alternate in a vertical direction between first gaps and second gaps. Overlapping conductive paths extend from the sense/access lines to the first circuitry. The conductive paths include first conductive interconnects within the first gaps and second conductive interconnects within the second gaps. The first and second conductive interconnects are laterally offset relative to one another.

公开(公告)号：US20220199123A1

公开(公告)日：2022-06-23

申请号：US17693119

申请日：2022-03-11

Applicant: Micron Technology, Inc.

Inventor： Raju Ahmed ,  David A. Kewley ,  Dave Pratt ,  Yung-Ta Sung ,  Frank Speetjens ,  Gurpreet Lugani

IPC: G11C5/06 ,  H01L23/532

Abstract: Some embodiments include an integrated assembly having an interconnect over a first conductive structure and coupled with the first conductive structure. The interconnect includes a conductive core. The conductive core has a slender upper region and a wide lower region. The upper region joins to the lower region at a step. A liner laterally surrounds the lower region of the conductive core. The liner has an upper surface which is substantially coplanar with the step. An insulative collar is over and directly against both an upper surface of the step and the upper surface of the liner. The insulative collar laterally surrounds and directly contacts the slender upper region. A second conductive structure is over and directly against a region of the insulative collar, and is over and directly against an upper surface of the slender upper region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11978527B2

公开(公告)日：2024-05-07

申请号：US17693119

申请日：2022-03-11

Applicant: Micron Technology, Inc.

Inventor： Raju Ahmed ,  David A. Kewley ,  Dave Pratt ,  Yung-Ta Sung ,  Frank Speetjens ,  Gurpreet Lugani

IPC: H01L23/532 ,  G11C5/06

CPC classification number: G11C5/06 ,  H01L23/53257 ,  H01L23/5329

Abstract: Some embodiments include an integrated assembly having an interconnect over a first conductive structure and coupled with the first conductive structure. The interconnect includes a conductive core. The conductive core has a slender upper region and a wide lower region. The upper region joins to the lower region at a step. A liner laterally surrounds the lower region of the conductive core. The liner has an upper surface which is substantially coplanar with the step. An insulative collar is over and directly against both an upper surface of the step and the upper surface of the liner. The insulative collar laterally surrounds and directly contacts the slender upper region. A second conductive structure is over and directly against a region of the insulative collar, and is over and directly against an upper surface of the slender upper region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20230335439A1

公开(公告)日：2023-10-19

申请号：US17720695

申请日：2022-04-14

Applicant: Micron Technology, Inc.

Inventor： Chandra S. Tiwari ,  David A. Kewley ,  Deep Panjwani ,  Matthew Holland ,  Matthew J. King ,  Michael E. Koltonski ,  Tom J. John ,  Xiaosong Zhang ,  Yi Hu

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76897 ,  H01L23/53295 ,  H01L21/76832 ,  H01L27/11521

Abstract: A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures. Memory cells vertically extend through the stack structure, and comprise a channel material vertically extending through the stack structure. An additional stack structure vertically overlies the stack structure and comprises additional conductive structures and additional insulative structures. First pillar structures extend through the additional stack structure and vertically overlie a portion of the memory cells. Second pillar structures are adjacent to the first pillar structures and extend through the additional stack structure and vertically overlie another portion of the memory cells. Slot structures are laterally adjacent to the first pillar structures and to the second pillar structures and extend through at least a portion of the additional stack structure. A distance between the first pillar structures and the slot structures is substantially equal to a distance between the second pillar structures and the slot structures.

公开(公告)号：US20230163030A1

公开(公告)日：2023-05-25

申请号：US18151378

申请日：2023-01-06

Applicant: Micron Technology, Inc.

Inventor： Trupti D. Gawai ,  David A. Kewley ,  Aaron M. Lowe ,  Radhakrishna Kotti ,  David S. Pratt

IPC: H01L21/768 ,  H01L23/535

CPC classification number: H01L21/76895 ,  H01L21/76805 ,  H01L23/535

Abstract: Methods of manufacturing semiconductor devices, and associated systems and devices, are disclosed herein. In some embodiments, a method of manufacturing a semiconductor device includes forming an opening in an insulative material at least partially over an electrically conductive feature. The method can further include forming a ring of electrically non-conductive material extending at least partially about a sidewall of the insulative material that defines the opening. The method can further include removing a portion of the ring to form an opening over the electrically conductive feature, and then depositing an electrically conductive material into the opening in the ring to form a conductive via electrically coupled to the electrically conductive feature.

公开(公告)号：US11574842B2

公开(公告)日：2023-02-07

申请号：US17230833

申请日：2021-04-14

Applicant: Micron Technology, Inc.

Inventor： Trupti D. Gawai ,  David A. Kewley ,  Aaron M. Lowe ,  Radhakrishna Kotti ,  David S. Pratt

IPC: H01L21/768 ,  H01L23/535

Abstract: Methods of manufacturing semiconductor devices, and associated systems and devices, are disclosed herein. In some embodiments, a method of manufacturing a semiconductor device includes forming an opening in an insulative material at least partially over an electrically conductive feature. The method can further include forming a ring of electrically non-conductive material extending at least partially about a sidewall of the insulative material that defines the opening. The method can further include removing a portion of the ring to form an opening over the electrically conductive feature, and then depositing an electrically conductive material into the opening in the ring to form a conductive via electrically coupled to the electrically conductive feature.

公开(公告)号：US11328749B2

公开(公告)日：2022-05-10

申请号：US16718454

申请日：2019-12-18

Applicant: Micron Technology, inc.

Inventor： Raju Ahmed ,  David A. Kewley ,  Dave Pratt ,  Yung-Ta Sung ,  Frank Speetjens ,  Gurpreet Lugani

IPC: H01L23/532 ,  G11C5/06

Abstract: Some embodiments include an integrated assembly having an interconnect over a first conductive structure and coupled with the first conductive structure. The interconnect includes a conductive core. The conductive core has a slender upper region and a wide lower region. The upper region joins to the lower region at a step. A liner laterally surrounds the lower region of the conductive core. The liner has an upper surface which is substantially coplanar with the step. An insulative collar is over and directly against both an upper surface of the step and the upper surface of the liner. The insulative collar laterally surrounds and directly contacts the slender upper region. A second conductive structure is over and directly against a region of the insulative collar, and is over and directly against an upper surface of the slender upper region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11101171B2

公开(公告)日：2021-08-24

申请号：US16542507

申请日：2019-08-16

Applicant: Micron Technology, Inc.

Inventor： Xiaosong Zhang ,  Yongjun J. Hu ,  David A. Kewley ,  Md Zahid Hossain ,  Michael J. Irwin ,  Daniel Billingsley ,  Suresh Ramarajan ,  Robert J. Hanson ,  Biow Hiem Ong ,  Keen Wah Chow

IPC: H01L21/768

Abstract: An apparatus comprises a structure including an upper insulating material overlying a lower insulating material, a conductive element underlying the lower insulating material, and a conductive material comprising a metal line and a contact. The conductive material extends from an upper surface of the upper insulating material to an upper surface of the conductive element. The structure also comprises a liner material adjacent the metal line. A width of an uppermost surface of the conductive material of the metal line external to the contact is relatively less than a width of an uppermost surface of the conductive material of the contact. Related methods, memory devices, and electronic systems are disclosed.