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    TECHNIQUES FOR FORMING MEMORY STRUCTURES
    2.
    发明申请
    TECHNIQUES FOR FORMING MEMORY STRUCTURES 有权

    公开(公告)号：US20210234097A1

    公开(公告)日：2021-07-29

    申请号：US17165549

    申请日：2021-02-02

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Gotti ,  Pavan Reddy K. Aella ,  Dale W. Collins

    IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

    Abstract: Methods, systems, and devices for techniques for forming memory structures are described. Forming a memory structure may include etching a stack of material including a conductive line, a first electrode and a sacrificial material to divide the stack of material into multiple sections. The process may further include depositing an oxide material in each of the first quantity of channels to form multiple oxide materials. The sacrificial material may be etched to form a second channel between two oxide materials of the multiple oxide materials. Memory material may be deposited over the two oxide materials and the second channel, which may create a void in the second channel between the memory material and the first electrode. The memory material may be heated to fill the void in the second channel.

    Semiconductor devices including liners, and related systems
    3.
    发明授权
    Semiconductor devices including liners, and related systems 有权

    公开(公告)号：US11038107B2

    公开(公告)日：2021-06-15

    申请号：US16202379

    申请日：2018-11-28

    Applicant: Micron Technology, Inc.

    Inventor： Dale W. Collins ,  Andrea Gotti ,  F. Daniel Gealy ,  Tuman E. Allen ,  Swapnil Lengade

    IPC: H01L45/00 ,  H01L27/24

    Abstract: A semiconductor structure includes a plurality of stack structures overlying a substrate. Each stack structure includes a first chalcogenide material over a conductive material overlying the substrate, an electrode over the first chalcogenide material, a second chalcogenide material over the electrode, a liner on sidewalls of at least one of the first chalcogenide material or the second chalcogenide material, and a dielectric material over and in contact with sidewalls of the electrode and in contact with the liner. Related semiconductor devices and systems, methods of forming the semiconductor structure, semiconductor device, and systems, and methods of forming the liner in situ are disclosed.

    Memory cells and semiconductor structures including electrodes comprising a metal, and related methods
    4.
    发明授权
    Memory cells and semiconductor structures including electrodes comprising a metal, and related methods 有权
    包含金属的电极的存储单元和半导体结构及相关方法

    公开(公告)号：US09553264B2

    公开(公告)日：2017-01-24

    申请号：US14726779

    申请日：2015-06-01

    Applicant: Micron Technology, Inc.

    Inventor： Dale W. Collins ,  Marko Milojevic ,  Scott E. Sills ,  Si-Young Park

    IPC: H01L45/00

    CPC classification number: H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/141 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16

    Abstract: Memory cells (e.g., CBRAM cells) include an ion source material over an active material and an electrode comprising metal silicide over the ion source material. The ion source material may include at least one of a chalcogenide material and a metal. Apparatuses, such as systems and devices, include a plurality of such memory cells. Memory cells include an adhesion material of metal silicide between a ion source material and an electrode of elemental metal. Methods of forming a memory cell include forming a first electrode, forming an active material, forming an ion source material, and forming a second electrode including metal silicide over the metal ion source material. Methods of adhering a material including copper and a material including tungsten include forming a tungsten silicide material over a material including copper and treating the materials.

    Abstract translation: 存储单元（例如，CBRAM单元）包括活性材料上的离子源材料和在离子源材料上的包含金属硅化物的电极。 离子源材料可以包括硫族化物材料和金属中的至少一种。 装置，例如系统和装置，包括多个这样的存储单元。 存储单元包括在离子源材料和元素金属电极之间的金属硅化物的粘附材料。 形成存储单元的方法包括形成第一电极，形成活性材料，形成离子源材料，以及在金属离子源材料上形成包括金属硅化物的第二电极。 包括铜和包括钨的材料的材料的粘合方法包括在包括铜的材料上形成硅化钨材料并处理材料。

    Methods for forming conductive vias, and associated devices and systems
    8.
    发明授权
    Methods for forming conductive vias, and associated devices and systems 有权

    公开(公告)号：US11515204B2

    公开(公告)日：2022-11-29

    申请号：US17136287

    申请日：2020-12-29

    Applicant: Micron Technology, Inc.

    Inventor： Trupti D. Gawai ,  David S. Pratt ,  Ahmed M. Elsied ,  David A. Kewley ,  Dale W. Collins ,  Raju Ahmed ,  Chelsea M. Jordan ,  Radhakrishna Kotti

    IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

    Abstract: Methods of manufacturing semiconductor devices, and associated systems and devices, are disclosed herein. In some embodiments, a method of manufacturing a semiconductor device includes forming an opening in an electrically insulative material at least partially over a first electrically conductive feature and a second electrically conductive feature. The method can further include forming a ring of electrically conductive material around a sidewall of the insulative material defining the opening, wherein the ring of electrically conductive material includes (a) a first via portion over the first electrically conductive feature, (b) a second via portion over the second electrically conductive feature, and (c) connecting portions extending between the first and second via portions. Finally, the method can include removing the connecting portions of the ring of electrically conductive material to electrically isolate the first via portion from the second via portion.

    METHODS FOR FORMING CONDUCTIVE VIAS, AND ASSOCIATED DEVICES AND SYSTEMS
    9.
    发明申请
    METHODS FOR FORMING CONDUCTIVE VIAS, AND ASSOCIATED DEVICES AND SYSTEMS 有权

    公开(公告)号：US20220208606A1

    公开(公告)日：2022-06-30

    申请号：US17136287

    申请日：2020-12-29

    Applicant: Micron Technology, Inc.

    Inventor： Trupti D. Gawai ,  David S. Pratt ,  Ahmed M. Elsied ,  David A. Kewley ,  Dale W. Collins ,  Raju Ahmed ,  Chelsea M. Jordan ,  Radhakrishna Kotti

    IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522

    Abstract: Methods of manufacturing semiconductor devices, and associated systems and devices, are disclosed herein. In some embodiments, a method of manufacturing a semiconductor device includes forming an opening in an electrically insulative material at least partially over a first electrically conductive feature and a second electrically conductive feature. The method can further include forming a ring of electrically conductive material around a sidewall of the insulative material defining the opening, wherein the ring of electrically conductive material includes (a) a first via portion over the first electrically conductive feature, (b) a second via portion over the second electrically conductive feature, and (c) connecting portions extending between the first and second via portions. Finally, the method can include removing the connecting portions of the ring of electrically conductive material to electrically isolate the first via portion from the second via portion.

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