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公开(公告)号：US12213325B2
公开(公告)日：2025-01-28
申请号：US17499709
申请日：2021-10-12
Applicant: Micron Technology, Inc.
Inventor： Anna Maria Conti , Andrea Gotti , Pavan Reddy K. Aella
Abstract: Methods, systems, and devices for techniques for manufacturing a double electrode memory array are described. A memory device may be fabricated using a sequence of fabrication steps that include depositing a first stack of materials including a conductive layer, an interface layer, and a first electrode layer. The first stack of materials may be etched to form a first set of trenches. A second stack of materials may be deposited on top of the first stack of materials. The second stack may include a second electrode layer in contact with the first electrode layer, a storage layer, and a third electrode layer. The second stack of materials may be etched to form a second set of trenches above the first set of trenches, and filled with a sealing layer and a dielectric material. The sealing layer may not extend substantially into the first set of trenches.
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公开(公告)号：US20210234097A1
公开(公告)日：2021-07-29
申请号：US17165549
申请日：2021-02-02
Applicant: Micron Technology, Inc.
Inventor： Andrea Gotti , Pavan Reddy K. Aella , Dale W. Collins
Abstract: Methods, systems, and devices for techniques for forming memory structures are described. Forming a memory structure may include etching a stack of material including a conductive line, a first electrode and a sacrificial material to divide the stack of material into multiple sections. The process may further include depositing an oxide material in each of the first quantity of channels to form multiple oxide materials. The sacrificial material may be etched to form a second channel between two oxide materials of the multiple oxide materials. Memory material may be deposited over the two oxide materials and the second channel, which may create a void in the second channel between the memory material and the first electrode. The memory material may be heated to fill the void in the second channel.
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公开(公告)号：US20230113960A1
公开(公告)日：2023-04-13
申请号：US17499709
申请日：2021-10-12
Applicant: Micron Technology, Inc.
Inventor： Anna Maria Conti , Andrea Gotti , Pavan Reddy K. Aella
Abstract: Methods, systems, and devices for techniques for manufacturing a double electrode memory array are described. A memory device may be fabricated using a sequence of fabrication steps that include depositing a first stack of materials including a conductive layer, an interface layer, and a first electrode layer. The first stack of materials may be etched to form a first set of trenches. A second stack of materials may be deposited on top of the first stack of materials. The second stack may include a second electrode layer in contact with the first electrode layer, a storage layer, and a third electrode layer. The second stack of materials may be etched to form a second set of trenches above the first set of trenches, and filled with a sealing layer and a dielectric material. The sealing layer may not extend substantially into the first set of trenches.
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公开(公告)号：US20220020446A1
公开(公告)日：2022-01-20
申请号：US17387290
申请日：2021-07-28
Applicant: Micron Technology, Inc.
Inventor： Amitava Majumdar , Radhakrishna Kotti , Patrick Daniel White , Pavan Reddy K. Aella , Rajesh Kamana
Abstract: Methods, systems, and devices for leakage source detection are described. In some cases, a testing device may scan a first set of access lines of a memory die that have a first length and a second set of access lines of the memory die that have a second length different than the first length. The testing device may determine a first error rate associated with the first set of access lines and a second error rate associated with the second set of access lines. The testing device may categorize a performance of the memory die based on the first and second error rates. In some cases, the testing device may determine a third error rate associated with a type of error based on the first and second error rates and may categorize the performance of the memory die based on the third error rate.
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公开(公告)号：US11575085B2
公开(公告)日：2023-02-07
申请号：US17165549
申请日：2021-02-02
Applicant: Micron Technology, Inc.
Inventor： Andrea Gotti , Pavan Reddy K. Aella , Dale W. Collins
Abstract: Methods, systems, and devices for techniques for forming memory structures are described. Forming a memory structure may include etching a stack of material including a conductive line, a first electrode and a sacrificial material to divide the stack of material into multiple sections. The process may further include depositing an oxide material in each of the first quantity of channels to form multiple oxide materials. The sacrificial material may be etched to form a second channel between two oxide materials of the multiple oxide materials. Memory material may be deposited over the two oxide materials and the second channel, which may create a void in the second channel between the memory material and the first electrode. The memory material may be heated to fill the void in the second channel.
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公开(公告)号：US20210151119A1
公开(公告)日：2021-05-20
申请号：US16684533
申请日：2019-11-14
Applicant: Micron Technology, Inc.
Inventor： Amitava Majumdar , Radhakrishna Kotti , Patrick Daniel White , Pavan Reddy K. Aella , Rajesh Kamana
Abstract: Methods, systems, and devices for leakage source detection are described. In some cases, a testing device may scan a first set of access lines of a memory die that have a first length and a second set of access lines of the memory die that have a second length different than the first length. The testing device may determine a first error rate associated with the first set of access lines and a second error rate associated with the second set of access lines. The testing device may categorize a performance of the memory die based on the first and second error rates. In some cases, the testing device may determine a third error rate associated with a type of error based on the first and second error rates and may categorize the performance of the memory die based on the third error rate.
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公开(公告)号：US10930849B2
公开(公告)日：2021-02-23
申请号：US16456349
申请日：2019-06-28
Applicant: Micron Technology, Inc.
Inventor： Andrea Gotti , Pavan Reddy K. Aella , Dale W. Collins
Abstract: Methods, systems, and devices for techniques for forming memory structures are described. Forming a memory structure may include etching a stack of material including a conductive line, a first electrode and a sacrificial material to divide the stack of material into multiple sections. The process may further include depositing an oxide material in each of the first quantity of channels to form multiple oxide materials. The sacrificial material may be etched to form a second channel between two oxide materials of the multiple oxide materials. Memory material may be deposited over the two oxide materials and the second channel, which may create a void in the second channel between the memory material and the first electrode. The memory material may be heated to fill the void in the second channel.
