公开(公告)号：US08927410B2

公开(公告)日：2015-01-06

申请号：US14100893

申请日：2013-12-09

Applicant: Micron Technology, Inc.

Inventor： Dave Pratt ,  Andy Perkins

IPC: H01L21/44 ,  H01L21/768

CPC classification number: H01L21/76898 ,  H01L21/02282 ,  H01L21/76831

Abstract: A method of forming a through substrate interconnect includes forming a via into a semiconductor substrate. The via extends into semiconductive material of the substrate. A liquid dielectric is applied to line at least an elevationally outermost portion of sidewalls of the via relative a side of the substrate from which the via was initially formed. The liquid dielectric is solidified within the via. Conductive material is formed within the via over the solidified dielectric and a through substrate interconnect is formed with the conductive material.

Abstract translation: 形成贯穿基板互连的方法包括将通孔形成为半导体基板。 通孔延伸到基板的半导体材料中。 施加液体电介质以将通孔的侧壁的至少顶部最外部分相对于基底的最初形成通孔的一侧排列。 液体电介质在通孔内固化。 导电材料形成在固化电介质上的通孔中，并且通过基板互连形成有导电材料。

公开(公告)号：US11978527B2

公开(公告)日：2024-05-07

申请号：US17693119

申请日：2022-03-11

Applicant: Micron Technology, Inc.

Inventor： Raju Ahmed ,  David A. Kewley ,  Dave Pratt ,  Yung-Ta Sung ,  Frank Speetjens ,  Gurpreet Lugani

IPC: H01L23/532 ,  G11C5/06

CPC classification number: G11C5/06 ,  H01L23/53257 ,  H01L23/5329

Abstract: Some embodiments include an integrated assembly having an interconnect over a first conductive structure and coupled with the first conductive structure. The interconnect includes a conductive core. The conductive core has a slender upper region and a wide lower region. The upper region joins to the lower region at a step. A liner laterally surrounds the lower region of the conductive core. The liner has an upper surface which is substantially coplanar with the step. An insulative collar is over and directly against both an upper surface of the step and the upper surface of the liner. The insulative collar laterally surrounds and directly contacts the slender upper region. A second conductive structure is over and directly against a region of the insulative collar, and is over and directly against an upper surface of the slender upper region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11545391B2

公开(公告)日：2023-01-03

申请号：US16787321

申请日：2020-02-11

Applicant: Micron Technology, Inc.

Inventor： Raju Ahmed ,  Frank Speetjens ,  Darin S. Miller ,  Siva Naga Sandeep Chalamalasetty ,  Dave Pratt ,  Yi Hu ,  Yung-Ta Sung ,  Aaron K. Belsher ,  Allen R. Gibson

IPC: H01L21/768 ,  H01L23/522

Abstract: Some embodiments include a method of forming an integrated assembly. An arrangement is formed to include a conductive pillar extending through an insulative mass. An upper surface of the conductive pillar is recessed to form a cavity. An insulative collar is formed within the cavity to line an outer lateral periphery of the cavity. A recessed surface of the conductive pillar is exposed at a bottom of the lined cavity. A conductive expanse is formed over the insulative mass. A portion of the conductive expanse extends into the cavity and is configured as an interconnect. The conductive expanse is patterned into multiple conductive structures. One of the conductive structures includes the interconnect.

公开(公告)号：US11328749B2

公开(公告)日：2022-05-10

申请号：US16718454

申请日：2019-12-18

Applicant: Micron Technology, inc.

Inventor： Raju Ahmed ,  David A. Kewley ,  Dave Pratt ,  Yung-Ta Sung ,  Frank Speetjens ,  Gurpreet Lugani

IPC: H01L23/532 ,  G11C5/06

Abstract: Some embodiments include an integrated assembly having an interconnect over a first conductive structure and coupled with the first conductive structure. The interconnect includes a conductive core. The conductive core has a slender upper region and a wide lower region. The upper region joins to the lower region at a step. A liner laterally surrounds the lower region of the conductive core. The liner has an upper surface which is substantially coplanar with the step. An insulative collar is over and directly against both an upper surface of the step and the upper surface of the liner. The insulative collar laterally surrounds and directly contacts the slender upper region. A second conductive structure is over and directly against a region of the insulative collar, and is over and directly against an upper surface of the slender upper region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20230021072A1

公开(公告)日：2023-01-19

申请号：US17947038

申请日：2022-09-16

Applicant: Micron Technology, Inc.

Inventor： Raju Ahmed ,  Radhakrishna Kotti ,  David A. Kewley ,  Dave Pratt

IPC: H01L23/528 ,  H01L23/522

Abstract: Some embodiments include an integrated assembly having a base which includes first circuitry. Memory decks are over the base. Each of the memory decks has a sense/access line coupled with the first circuitry. The memory decks and base are vertically spaced from one another by gaps. The gaps alternate in a vertical direction between first gaps and second gaps. Overlapping conductive paths extend from the sense/access lines to the first circuitry. The conductive paths include first conductive interconnects within the first gaps and second conductive interconnects within the second gaps. The first and second conductive interconnects are laterally offset relative to one another.

公开(公告)号：US20220013449A1

公开(公告)日：2022-01-13

申请号：US16925767

申请日：2020-07-10

Applicant: Micron Technology, Inc.

Inventor： Raju Ahmed ,  Radhakrishna Kotti ,  David A. Kewley ,  Dave Pratt

IPC: H01L23/528 ,  H01L23/522

Abstract: Some embodiments include an integrated assembly having a base which includes first circuitry. Memory decks are over the base. Each of the memory decks has a sense/access line coupled with the first circuitry. The memory decks and base are vertically spaced from one another by gaps. The gaps alternate in a vertical direction between first gaps and second gaps. Overlapping conductive paths extend from the sense/access lines to the first circuitry. The conductive paths include first conductive interconnects within the first gaps and second conductive interconnects within the second gaps. The first and second conductive interconnects are laterally offset relative to one another.

公开(公告)号：US20170256452A1

公开(公告)日：2017-09-07

申请号：US15602627

申请日：2017-05-23

Applicant: Micron Technology, Inc.

Inventor： Dave Pratt ,  Andy Perkins

IPC: H01L21/768 ,  H01L21/02

Abstract: A method of forming a through substrate interconnect includes forming a via into a semiconductor substrate. The via extends into semiconductive material of the substrate. A liquid dielectric is applied to line at least an elevationally outermost portion of sidewalls of the via relative a side of the substrate from which the via was initially formed. The liquid dielectric is solidified within the via. Conductive material is formed within the via over the solidified dielectric and a through substrate interconnect is formed with the conductive material.

公开(公告)号：US20150087147A1

公开(公告)日：2015-03-26

申请号：US14561642

申请日：2014-12-05

Applicant: Micron Technology, Inc.

Inventor： Dave Pratt ,  Andy Perkins

IPC: H01L21/768 ,  H01L21/02

CPC classification number: H01L21/76898 ,  H01L21/02282 ,  H01L21/76831

Abstract: A method of forming a through substrate interconnect includes forming a via into a semiconductor substrate. The via extends into semiconductive material of the substrate. A liquid dielectric is applied to line at least an elevationally outermost portion of sidewalls of the via relative a side of the substrate from which the via was initially formed. The liquid dielectric is solidified within the via. Conductive material is formed within the via over the solidified dielectric and a through substrate interconnect is formed with the conductive material.

公开(公告)号：US20140099786A1

公开(公告)日：2014-04-10

申请号：US14100893

申请日：2013-12-09

Applicant: Micron Technology, Inc.

Inventor： Dave Pratt ,  Andy Perkins

IPC: H01L21/768

CPC classification number: H01L21/76898 ,  H01L21/02282 ,  H01L21/76831

Abstract: A method of forming a through substrate interconnect includes forming a via into a semiconductor substrate. The via extends into semiconductive material of the substrate. A liquid dielectric is applied to line at least an elevationally outermost portion of sidewalls of the via relative a side of the substrate from which the via was initially formed. The liquid dielectric is solidified within the via. Conductive material is formed within the via over the solidified dielectric and a through substrate interconnect is formed with the conductive material.

Abstract translation: 形成贯穿基板互连的方法包括将通孔形成为半导体基板。 通孔延伸到基板的半导体材料中。 施加液体电介质以将通孔的侧壁的至少顶部最外部分相对于基底的最初形成通孔的一侧排列。 液体电介质在通孔内固化。 导电材料形成在固化电介质上的通孔中，并且通过基板互连形成有导电材料。

公开(公告)号：US12014983B2

公开(公告)日：2024-06-18

申请号：US17947038

申请日：2022-09-16

Applicant: Micron Technology, Inc.

Inventor： Raju Ahmed ,  Radhakrishna Kotti ,  David A. Kewley ,  Dave Pratt

IPC: H01L23/528 ,  H01L23/522 ,  H10B61/00 ,  H10B63/00

CPC classification number: H01L23/528 ,  H01L23/5226 ,  H10B61/00 ,  H10B63/84

Abstract: Some embodiments include an integrated assembly having a base which includes first circuitry. Memory decks are over the base. Each of the memory decks has a sense/access line coupled with the first circuitry. The memory decks and base are vertically spaced from one another by gaps. The gaps alternate in a vertical direction between first gaps and second gaps. Overlapping conductive paths extend from the sense/access lines to the first circuitry. The conductive paths include first conductive interconnects within the first gaps and second conductive interconnects within the second gaps. The first and second conductive interconnects are laterally offset relative to one another.