公开(公告)号：US20210041495A1

公开(公告)日：2021-02-11

申请号：US17083193

申请日：2020-10-28

Applicant: Micron Technology, Inc.

Inventor： Tony M. Lindenberg ,  Kurt J. Bossart ,  Jonathan S. Hacker ,  Chandra S. Tiwari

IPC: G01R31/28 ,  H01L21/67 ,  G01R1/073 ,  H01L21/68

Abstract: A testing probe apparatus for testing die. The testing probe may include a probe interface and a carrier for supporting at least one die comprising 3D interconnect (3DI) structures. The probe interface may be positionable on a first side of the at least one die and include a voltage source and at least one first inductor operably coupled to the voltage source. A voltage sensor and at least one second inductor coupled to the voltage sensor may be disposed on a second opposing side of the at least one die. The voltage source of the probe interface may be configured to inductively cause a voltage within the 3DI structures of the at least one die via the at least one first inductor. The voltage sensor may be configured to sense a voltage within the at least one 3DI structure via the at least one second inductor. Related systems and methods are also disclosed.

公开(公告)号：US10790251B2

公开(公告)日：2020-09-29

申请号：US16013237

申请日：2018-06-20

Applicant: Micron Technology, Inc.

Inventor： Christopher J. Gambee ,  Nhi Doan ,  Chandra S. Tiwari ,  Owen R. Fay ,  Ying Chen

IPC: H01L23/00 ,  H01L21/027 ,  H01L21/56

Abstract: Methods of forming supports for 3D structures on semiconductor structures comprise forming the supports from photodefinable materials by deposition, selective exposure and curing. Semiconductor dice including 3D structures having associated supports, and semiconductor devices are also disclosed.

公开(公告)号：US20190341378A1

公开(公告)日：2019-11-07

申请号：US16514159

申请日：2019-07-17

Applicant: Micron Technology, Inc.

Inventor： Chandra S. Tiwari ,  Tony M. Lindenberg ,  Jonathan S. Hacker ,  Christopher J. Gambee ,  Kurt J. Bossart

IPC: H01L25/00 ,  H01L23/00 ,  H01L21/02 ,  H01L21/683

Abstract: A semiconductor device assembly that includes a first side of a semiconductor device supported on a substrate to permit the processing of a second side of the semiconductor device. A filler material deposited on the semiconductor device supports the semiconductor device on the substrate. The filler material does not adhere to the semiconductor device or the substrate. Alternatively, the filler material may be deposited on the substrate. Instead of a filler material, the substrate may include a topography configured to support the semiconductor device. Adhesive applied between an outer edge of the first side of the semiconductor and the substrate bonds the outer edge of the semiconductor device to the substrate to form a semiconductor device assembly. A second side of the semiconductor device may then be processed and the outer edge of the semiconductor device may be cut off to release the semiconductor device from the assembly.

公开(公告)号：US12205900B2

公开(公告)日：2025-01-21

申请号：US17664385

申请日：2022-05-20

Applicant: Micron Technology, Inc.

Inventor： Jivaan Kishore Jhothiraman ,  Rutuparna Narulkar ,  Chandra S. Tiwari

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/02 ,  H10B69/00

Abstract: An electronic device includes a stack structure, the stack structure including at least one deck including tiers of vertically alternating dielectric materials and conductive materials, an opening extending through the at least one deck, a compressive dielectric material disposed on a bottom surface defining the opening and on sidewalls of the tiers defining the opening, and a dielectric material in direct contact with the compressive dielectric material. The dielectric material substantially fills a remainder of the opening. The compressive dielectric material exhibits a horizontal compressive force against the tiers. Related methods and systems are also disclosed.

公开(公告)号：US20230378069A1

公开(公告)日：2023-11-23

申请号：US17664385

申请日：2022-05-20

Applicant: Micron Technology, Inc.

Inventor： Jivaan Kishore Jhothiraman ,  Rutuparna Narulkar ,  Chandra S. Tiwari

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53295 ,  H01L21/76837 ,  H01L27/115

Abstract: An electronic device includes a stack structure, the stack structure including at least one deck including tiers of vertically alternating dielectric materials and conductive materials, an opening extending through the at least one deck, a compressive dielectric material disposed on a bottom surface defining the opening and on sidewalls of the tiers defining the opening, and a dielectric material in direct contact with the compressive dielectric material. The dielectric material substantially fills a remainder of the opening. The compressive dielectric material exhibits a horizontal compressive force against the tiers. Related methods and systems are also disclosed.

公开(公告)号：US20230335439A1

公开(公告)日：2023-10-19

申请号：US17720695

申请日：2022-04-14

Applicant: Micron Technology, Inc.

Inventor： Chandra S. Tiwari ,  David A. Kewley ,  Deep Panjwani ,  Matthew Holland ,  Matthew J. King ,  Michael E. Koltonski ,  Tom J. John ,  Xiaosong Zhang ,  Yi Hu

IPC: H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76897 ,  H01L23/53295 ,  H01L21/76832 ,  H01L27/11521

Abstract: A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures. Memory cells vertically extend through the stack structure, and comprise a channel material vertically extending through the stack structure. An additional stack structure vertically overlies the stack structure and comprises additional conductive structures and additional insulative structures. First pillar structures extend through the additional stack structure and vertically overlie a portion of the memory cells. Second pillar structures are adjacent to the first pillar structures and extend through the additional stack structure and vertically overlie another portion of the memory cells. Slot structures are laterally adjacent to the first pillar structures and to the second pillar structures and extend through at least a portion of the additional stack structure. A distance between the first pillar structures and the slot structures is substantially equal to a distance between the second pillar structures and the slot structures.

公开(公告)号：US10262961B2

公开(公告)日：2019-04-16

申请号：US15982129

申请日：2018-05-17

Applicant: Micron Technology, Inc.

Inventor： Mayukhee Das ,  Jonathan S. Hacker ,  Christopher J. Gambee ,  Chandra S. Tiwari

IPC: H01L23/00 ,  H01L25/065 ,  H01L21/66

Abstract: Semiconductor devices having discretely located passivation material are disclosed herein. In one embodiment, a semiconductor device assembly can include a bond pad having a bonding surface with a process artifact. A passivation material can be positioned to at least partially fill a portion of the process artifact. A conductive structure can be positioned to extend across the bonding surface of the bond pad.

公开(公告)号：US20240071819A1

公开(公告)日：2024-02-29

申请号：US18234111

申请日：2023-08-15

Applicant: Micron Technology, Inc.

Inventor： Chandra S. Tiwari ,  Jivaan Kishore Jhothiraman ,  Rutuparna Narulkar ,  Nayan Chakravarty ,  Pengyuan Zheng ,  Hiroaki Iuchi

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76831 ,  H01L23/5226 ,  H10B43/27

Abstract: A variety of applications can include apparatus having a memory device structured with a three-dimensional array of memory cells and one or more vertical metal contacts extending through levels of the memory device, where the one or more vertical metal contacts are formed with reduced stress. Each of the one or more vertical metal contacts can be constructed by forming a liner on walls of an opening in a dielectric, where the opening extends through the levels for the memory device, and forming a metal composition adjacent the liner and filling the opening with the metal composition. The liner can be removed from at least a portion of the walls of the dielectric, where the liner has a composition correlated to the metal composition such that removal of the liner reduces stress on the metal composition.

公开(公告)号：US11476268B2

公开(公告)日：2022-10-18

申请号：US16887178

申请日：2020-05-29

Applicant: Micron Technology, Inc.

Inventor： Chandra S. Tiwari ,  Kunal Shrotri

IPC: H01L27/11556 ,  H01L27/11585 ,  H01L27/11519

Abstract: A method comprising forming a stack precursor comprising alternating first materials and second materials, the first materials and the second materials exhibit different melting points. A portion of the alternating first materials and second materials is removed to form a pillar opening through the alternating first materials and second materials. A sacrificial material is formed in the pillar opening. The first materials are removed to form first spaces between the second materials, the first materials formulated to be in a liquid phase or in a gas phase at a first removal temperature. A conductive material is formed in the first spaces. The second materials are removed to form second spaces between the conductive materials, the second materials formulated to be in a liquid phase or in a gas phase at a second removal temperature. A dielectric material is formed in the second spaces. The sacrificial material is removed from the pillar opening and cell materials are formed in the pillar opening.

公开(公告)号：US11322516B2

公开(公告)日：2022-05-03

申请号：US17007951

申请日：2020-08-31

Applicant: Micron Technology, Inc.

Inventor： Matthew J. King ,  David A. Daycock ,  Yoshiaki Fukuzumi ,  Albert Fayrushin ,  Richard J. Hill ,  Chandra S. Tiwari ,  Jun Fujiki

IPC: H01L27/11582 ,  H01L21/762 ,  H01L29/06

Abstract: Microelectronic devices include a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A series of pillars extends through the stack structure. At least one isolation structure extends through an upper stack portion of the stack structure. The at least one isolation structure protrudes into pillars of neighboring columns of pillars of the series of pillars. Conductive contacts are in electrical communication with the pillars into which the at least one isolation structure protrudes. Related methods and electronic systems are also disclosed.