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公开(公告)号：US11744086B2
公开(公告)日：2023-08-29
申请号：US17171622
申请日：2021-02-09
Applicant: Micron Technology, Inc.
Inventor： David A. Daycock , Jonghun Kim
CPC classification number: H10B63/84 , H10N70/023 , H10N70/026 , H10N70/8265 , H10N70/881
Abstract: A method of forming an electronic device comprises forming a stack structure comprising vertically alternating insulative structures and additional insulative structures, and forming pillars comprising a channel material and at least one dielectric material vertically extending through the stack structure. The method comprises removing the additional insulative structures to form cell openings, forming a first conductive material within a portion of the cell openings, and forming a fill material adjacent to the first conductive material and within the cell openings. The fill material comprises sacrificial portions. The method comprises removing the sacrificial portions of the fill material, and forming a second conductive material within the cell openings in locations previously occupied by the sacrificial portions of the fill material. Related electronic devices, memory devices, and systems are also described.
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公开(公告)号：US20230026960A1
公开(公告)日：2023-01-26
申请号：US17956797
申请日：2022-09-29
Applicant: Micron Technology, Inc.
Inventor： Bharat Bhushan , Pratap Murali , Raj K. Bansal , David A. Daycock
Abstract: A memory device includes a package substrate and at least one stack of a plurality of semiconductor dies disposed on the package substrate. The plurality of semiconductor dies can be stacked in a shingled configuration. Each semiconductor die includes a plurality of slits disposed in a first direction. An offset direction defining the shingled arrangement is in-line with the first direction. Each semiconductor die can include a die substrate and a plurality of memory planes disposed on the die substrate with each memory plane having a memory cell array. Each slit can divide and separate each memory plane into at least one of logic blocks or sub-logic blocks. The semiconductor die can include a plurality of bond pads linearly aligned in a second direction that is perpendicular to the first direction.
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公开(公告)号：US11158577B2
公开(公告)日：2021-10-26
申请号：US16778346
申请日：2020-01-31
Applicant: Micron Technology, Inc.
Inventor： Biow Hiem Ong , David A. Daycock , Chieh Hsien Quek , Chii Wean Calvin Chen , Christian George Emor , Wing Yu Lo
IPC: H01L23/535 , H01L21/768 , H01L23/522 , H01L23/528 , H01L23/532 , H01L27/11526 , H01L27/11582 , H01L27/11556
Abstract: Methods for forming microelectronic devices include forming a staircase structure in a stack structure having a vertically alternating sequence of insulative and conductive materials arranged in tiers. Steps are at lateral ends of the tiers. Contact openings of different aspect ratios are formed in fill material adjacent the staircase structure, with some openings terminating in the fill material and others exposing portions of the conductive material of upper tiers of the stack structure. Additional conductive material is selectively formed on the exposed portions of the conductive material. The contact openings initially terminating in the fill material are extended to expose portions of the conductive material of lower elevations. Contacts are formed, with some extending to the additional conductive material and others extending to conductive material of the tiers of the lower elevations. Microelectronic devices and systems incorporating such staircase structures and contacts are also disclosed.
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公开(公告)号：US20160027882A1
公开(公告)日：2016-01-28
申请号：US14875493
申请日：2015-10-05
Applicant: Micron Technology, Inc.
Inventor： Christopher J. Larsen , David A. Daycock , Kunal Shrotri
IPC: H01L29/423 , H01L29/788 , H01L29/06 , H01L27/115
CPC classification number: H01L29/42324 , H01L21/02164 , H01L21/0228 , H01L21/02337 , H01L21/3085 , H01L21/3086 , H01L21/32139 , H01L27/11517 , H01L27/11521 , H01L27/11558 , H01L29/0649 , H01L29/40114 , H01L29/788
Abstract: Methods of forming semiconductor devices, memory cells, and arrays of memory cells include forming a liner on a conductive material and exposing the liner to a radical oxidation process to densify the liner. The densified liner may protect the conductive material from substantial degradation or damage during a subsequent patterning process. A semiconductor device structure, according to embodiments of the disclosure, includes features extending from a substrate and spaced by a trench exposing a portion of a substrate. A liner is disposed on sidewalls of a region of at least one conductive material in each feature. A semiconductor device, according to embodiments of the disclosure, includes memory cells, each comprising a control gate region and a capping region with substantially aligning sidewalls and a charge structure under the control gate region.
Abstract translation: 形成半导体器件，存储器单元和存储器单元阵列的方法包括在导电材料上形成衬垫并将衬套暴露于自由基氧化工艺以使衬垫致密化。 致密的衬垫可以保护导电材料在随后的图案化工艺期间免受实质的劣化或损坏。 根据本公开的实施例的半导体器件结构包括从衬底延伸并由暴露衬底的一部分的沟槽间隔开的特征。 衬垫设置在每个特征中的至少一个导电材料的区域的侧壁上。 根据本公开的实施例的半导体器件包括存储器单元，每个存储器单元包括控制栅极区域和具有基本对准侧壁的封盖区域和在控制栅极区域下方的电荷结构。
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公开(公告)号：US20250048614A1
公开(公告)日：2025-02-06
申请号：US18745962
申请日：2024-06-17
Applicant: Micron Technology, Inc.
Inventor： Fatma Arzum Simsek-Ege , David A. Daycock , Christopher K. Morzano
IPC: H10B12/00
Abstract: A microelectronic device comprises a first transistor structure comprising multiple vertical levels of channel regions, a second transistor structure neighboring the first transistor structure and comprising additional multiple vertical levels of channel regions, a storage device vertically overlying the first transistor structure and the second transistor structure, a first conductive contact structure contacting the first transistor structure, and a second conductive contact structure contacting the second transistor structure. Related memory devices and electronic systems are also described.
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公开(公告)号：US11967556B2
公开(公告)日：2024-04-23
申请号：US17452113
申请日：2021-10-25
Applicant: Micron Technology, Inc.
Inventor： Biow Hiem Ong , David A. Daycock , Chieh Hsien Quek , Chii Wean Calvin Chen , Christian George Emor , Wing Yu Lo
IPC: H01L23/535 , H01L21/768 , H01L23/522 , H01L23/528 , H01L23/532 , H10B41/27 , H10B41/40 , H10B43/27
CPC classification number: H01L23/535 , H01L21/76805 , H01L21/76816 , H01L21/76843 , H01L21/76877 , H01L21/76895 , H01L23/5226 , H01L23/5283 , H01L23/53266 , H10B41/40 , H10B41/27 , H10B43/27
Abstract: Methods for forming microelectronic devices include forming a staircase structure in a stack structure having a vertically alternating sequence of insulative and conductive materials arranged in tiers. Steps are at lateral ends of the tiers. Contact openings of different aspect ratios are formed in fill material adjacent the staircase structure, with some openings terminating in the fill material and others exposing portions of the conductive material of upper tiers of the stack structure. Additional conductive material is selectively formed on the exposed portions of the conductive material. The contact openings initially terminating in the fill material are extended to expose portions of the conductive material of lower elevations. Contacts are formed, with some extending to the additional conductive material and others extending to conductive material of the tiers of the lower elevations. Microelectronic devices and systems incorporating such staircase structures and contacts are also disclosed.
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公开(公告)号：US20230380193A1
公开(公告)日：2023-11-23
申请号：US18365850
申请日：2023-08-04
Applicant: Micron Technology, Inc.
Inventor： David A. Daycock , Jonghun Kim
CPC classification number: H10B63/84 , H10N70/023 , H10N70/026 , H10N70/881 , H10N70/8265
Abstract: A method of forming an electronic device comprises forming a stack structure comprising vertically alternating insulative structures and additional insulative structures, and forming pillars comprising a channel material and at least one dielectric material vertically extending through the stack structure. The method comprises removing the additional insulative structures to form cell openings, forming a first conductive material within a portion of the cell openings, and forming a fill material adjacent to the first conductive material and within the cell openings. The fill material comprises sacrificial portions. The method comprises removing the sacrificial portions of the fill material, and forming a second conductive material within the cell openings in locations previously occupied by the sacrificial portions of the fill material. Related electronic devices, memory devices, and systems are also described.
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公开(公告)号：US20220262820A1
公开(公告)日：2022-08-18
申请号：US17661659
申请日：2022-05-02
Applicant: Micron Technology, Inc.
Inventor： Matthew J. King , David A. Daycock , Yoshiaki Fukuzumi , Albert Fayrushin , Richard J. Hill , Chandra S. Tiwari , Jun Fujiki
IPC: H01L27/11582 , H01L29/06 , H01L21/762
Abstract: Microelectronic devices include a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A series of pillars extends through the stack structure. At least one isolation structure extends through an upper stack portion of the stack structure. The at least one isolation structure protrudes into pillars of neighboring columns of pillars of the series of pillars. Conductive contacts are in electrical communication with the pillars into which the at least one isolation structure protrudes. Related methods and electronic systems are also disclosed.
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公开(公告)号：US11355607B2
公开(公告)日：2022-06-07
申请号：US14875493
申请日：2015-10-05
Applicant: Micron Technology, Inc.
Inventor： Christopher J. Larsen , David A. Daycock , Kunal Shrotri
IPC: H01L27/11521 , H01L29/788 , H01L29/423 , H01L21/308 , H01L27/11517 , H01L21/28 , H01L21/3213 , H01L27/11558 , H01L29/06 , H01L21/02
Abstract: Methods of forming semiconductor devices, memory cells, and arrays of memory cells include forming a liner on a conductive material and exposing the liner to a radical oxidation process to densify the liner. The densified liner may protect the conductive material from substantial degradation or damage during a subsequent patterning process. A semiconductor device structure, according to embodiments of the disclosure, includes features extending from a substrate and spaced by a trench exposing a portion of a substrate. A liner is disposed on sidewalls of a region of at least one conductive material in each feature. A semiconductor device, according to embodiments of the disclosure, includes memory cells, each comprising a control gate region and a capping region with substantially aligning sidewalls and a charge structure under the control gate region.
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公开(公告)号：US20240188299A1
公开(公告)日：2024-06-06
申请号：US18525362
申请日：2023-11-30
Applicant: Micron Technology, Inc.
Inventor： Christopher J. Larsen , S M Istiaque Hossain , David A. Daycock , Kevin R. Gast , George Matamis , Lingyu Kong , Sok Han Wong , Lhaang Chee Ooi , Wenjie Li
CPC classification number: H10B43/27 , G11C16/0483 , H10B43/10 , H10B43/35
Abstract: Methods, systems, and devices for three-dimensional memory array formation techniques are described. A memory device may include a stack of materials over a substrate. The memory device may include an array of first pillars and an array of second pillars extending at least partially through the stack of materials. One or more first pillars may be excluded from one or more columns of pillars of the array first pillars. The memory device may include dielectric material in a slit extending at least partially through the stack of materials. Based on the exclusion of the one or more first pillars, the slit may have a greater width at a first portion through the stack of materials than a second portion through the stack of materials. The dielectric material located in the slit may also have a greater width at the first portion than at the second portion.
