公开(公告)号：US20240379157A1

公开(公告)日：2024-11-14

申请号：US18741193

申请日：2024-06-12

Applicant: Micron Technology, Inc.

Inventor： Koushik Banerjee ,  Isaiah O. Gyan ,  Robert Cassel ,  Jian Jiao ,  William L. Cooper ,  Jason R. Johnson ,  Michael P. O'Toole

IPC: G11C13/00

Abstract: Methods, systems, and devices supporting configurable resistivities for lines in a memory device, such as access lines in a memory array are described. For example, metal lines at different levels of a memory device may be oxidized to different extents in order for the lines at different levels of the memory device to have different resistivities. This may allow the resistivity of lines to be tuned on a level-by-level basis without altering the fabrication techniques and related parameters used to initially form the lines at the different levels, which may have benefits related to at least reduced cost and complexity. Lines may be oxidized to a controlled extent using either a dry or wet process.

公开(公告)号：US20210241828A1

公开(公告)日：2021-08-05

申请号：US16781975

申请日：2020-02-04

Applicant: Micron Technology, Inc.

Inventor： Koushik Banerjee ,  Isaiah O. Gyan ,  Robert Cassel ,  Jian Jiao ,  William L. Cooper ,  Jason R. Johnson ,  Michael P. O'Toole

IPC: G11C13/00

Abstract: Methods, systems, and devices supporting configurable resistivities for lines in a memory device, such as access lines in a memory array are described. For example, metal lines at different levels of a memory device may be oxidized to different extents in order for the lines at different levels of the memory device to have different resistivities. This may allow the resistivity of lines to be tuned on a level-by-level basis without altering the fabrication techniques and related parameters used to initially form the lines at the different levels, which may have benefits related to at least reduced cost and complexity. Lines may be oxidized to a controlled extent using either a dry or wet process.

公开(公告)号：US12040014B2

公开(公告)日：2024-07-16

申请号：US17970756

申请日：2022-10-21

Applicant: Micron Technology, Inc.

Inventor： Koushik Banerjee ,  Isaiah O. Gyan ,  Robert Cassel ,  Jian Jiao ,  William L. Cooper ,  Jason R. Johnson ,  Michael P. O'Toole

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/003 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/71 ,  G11C2213/79

Abstract: Methods, systems, and devices supporting configurable resistivities for lines in a memory device, such as access lines in a memory array are described. For example, metal lines at different levels of a memory device may be oxidized to different extents in order for the lines at different levels of the memory device to have different resistivities. This may allow the resistivity of lines to be tuned on a level-by-level basis without altering the fabrication techniques and related parameters used to initially form the lines at the different levels, which may have benefits related to at least reduced cost and complexity. Lines may be oxidized to a controlled extent using either a dry or wet process.

公开(公告)号：US11495293B2

公开(公告)日：2022-11-08

申请号：US16781975

申请日：2020-02-04

Applicant: Micron Technology, Inc.

Inventor： Koushik Banerjee ,  Isaiah O. Gyan ,  Robert Cassel ,  Jian Jiao ,  William L. Cooper ,  Jason R. Johnson ,  Michael P. O'Toole

IPC: G11C11/00 ,  G11C13/00

Abstract: Methods, systems, and devices supporting configurable resistivities for lines in a memory device, such as access lines in a memory array are described. For example, metal lines at different levels of a memory device may be oxidized to different extents in order for the lines at different levels of the memory device to have different resistivities. This may allow the resistivity of lines to be tuned on a level-by-level basis without altering the fabrication techniques and related parameters used to initially form the lines at the different levels, which may have benefits related to at least reduced cost and complexity. Lines may be oxidized to a controlled extent using either a dry or wet process.

公开(公告)号：US20230114440A1

公开(公告)日：2023-04-13

申请号：US17970756

申请日：2022-10-21

Applicant: Micron Technology, Inc.

Inventor： Koushik Banerjee ,  Isaiah O. Gyan ,  Robert Cassel ,  Jian Jiao ,  William L. Cooper ,  Jason R. Johnson ,  Michael P. O'Toole

IPC: G11C13/00

Abstract: Methods, systems, and devices supporting configurable resistivities for lines in a memory device, such as access lines in a memory array are described. For example, metal lines at different levels of a memory device may be oxidized to different extents in order for the lines at different levels of the memory device to have different resistivities. This may allow the resistivity of lines to be tuned on a level-by-level basis without altering the fabrication techniques and related parameters used to initially form the lines at the different levels, which may have benefits related to at least reduced cost and complexity. Lines may be oxidized to a controlled extent using either a dry or wet process.