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公开(公告)号：US20240349624A1
公开(公告)日：2024-10-17
申请号：US18034489
申请日：2021-10-28
CPC分类号： H10N52/101 , H01L23/66 , H10N50/85 , H10N52/80 , H10N59/00 , H01L2223/6677
摘要： A rectifier device, has a Hall layer comprising a layer of a Hall material, and a spin-orbit layer adjacent the Hall layer. The spin-orbit layer has a spin-orbit material having a first surface and a second surface, a ferromagnet adjacent the spin-orbit material, and oxide on the outer surfaces of the spin-orbit layer. A rectifying system has an array of the above rectifying devices having a number, K, of parallel branches, each branch having N devices, branch electrical connections between corresponding devices in each of the parallel branches, and device electrical connection between devices in each parallel branch.
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2.发明公开公开(公告)号：US20240224815A1
公开(公告)日：2024-07-04
申请号：US18392467
申请日：2023-12-21
发明人： Guido DUPONT , Daniel ROSENFELD , Lionel TOMBEZ , Appo VAN DER WIEL , Gael CLOSE
CPC分类号： H10N52/80 , G01R33/0011 , G01R33/07 , H10N50/80 , H10N52/01 , H10N52/101 , H10N59/00
摘要： A semiconductor device includes a semiconductor substrate, having an excitation circuit for applying an excitation signal, and a soft-magnetic component for guiding magnetic flux lines. The soft-magnetic component is electrically connected to the excitation by at least two electrical contacts in the form of back contacts or side contacts. The substrate further includes at least one electromagnetic transducer operatively connected to the soft-magnetic component. The excitation circuit includes a modulator for providing a modulated signal to the soft-magnetic component to modulate its magnetic permeability. The substrate further has a demodulator configured to demodulate signals obtained from the at least one electromagnetic transducer.
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公开(公告)号：US20240319234A1
公开(公告)日：2024-09-26
申请号：US18737108
申请日：2024-06-07
发明人： Dok Won Lee , Jo Bito , Keith Ryan Green
CPC分类号： G01R15/207 , G01R15/202 , H01L23/49586 , H10N52/00 , H10N52/80 , H10B61/00 , H10N59/00
摘要： In one example, a device comprises a lead frame, a semiconductor die, a spacer, and a magnetic concentrator. The lead frame comprises a conductor. The spacer is between the semiconductor die and the conductor. The magnetic concentrator overlaps at least partially with the conductor.
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公开(公告)号：US12069956B2
公开(公告)日：2024-08-20
申请号：US17487877
申请日：2021-09-28
CPC分类号： H10N50/01 , G01R33/0052 , G01R33/096 , H01L21/30604 , H10N50/10 , H10N50/80 , H10N59/00
摘要： Apparatus, and their methods of manufacture, including an integrated circuit device having metallization layers for interconnecting underlying electronic devices. Contacts contact conductors of an uppermost one of the metallization layers. A planarized first dielectric layer covers the contacts and the uppermost one of the metallization layers. An anisotropic magnetoresistive (AMR) stack is on the first dielectric layer between vertically aligned portions of an etch stop layer formed on the first dielectric layer and a second dielectric layer formed on the etch stop layer. Vias extend through the first dielectric layer to electrically connect the AMR stack and the contacts. A chemical-mechanical planarization (CMP) stop layer is on the AMR stack. A third dielectric layer is on the CMP stop layer. A passivation layer contacts the second dielectric layer portions, the third dielectric layer, and each opposing end of the AMR stack and the CMP stop layer.
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公开(公告)号：US12058872B2
公开(公告)日：2024-08-06
申请号：US17207236
申请日：2021-03-19
申请人： TDK CORPORATION
发明人： Shogo Yamada , Tatsuo Shibata , Tomoyuki Sasaki
IPC分类号： H01L27/22 , G06N3/063 , G06N3/065 , G06N3/08 , G11C11/16 , G11C11/54 , H01L43/02 , H01L43/08 , H10B61/00 , H10N50/10 , H10N50/80 , H10N59/00 , G06N3/044
CPC分类号： H10B61/00 , G06N3/063 , G06N3/065 , G06N3/08 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/54 , H10B61/22 , H10N50/10 , H10N50/80 , H10N59/00 , G06N3/044
摘要： An integrated device includes: a substrate; and a laminated structural body. The substrate has a plurality of switching elements. The laminated structural body has a plurality of magnetic elements having a first element group disposed in a first hierarchical layer and a second element group disposed in a second hierarchical layer. Each of the plurality of magnetic elements includes a conductive layer and a laminated body including a ferromagnetic layer. The plurality of switching elements include a plurality of first switching elements connected to first ends of the conductive layers and a plurality of second switching elements connected to second ends of the conductive layers. A first switching element connected to a second magnetic element belonging to a second element group which is present between a first switching element and a second switching element connected to a first magnetic element belonging to a first element group.
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公开(公告)号：US20240008371A1
公开(公告)日：2024-01-04
申请号：US18295269
申请日：2023-04-04
发明人： Keita OKADA , Ryota SAKAMOTO
CPC分类号： H10N59/00 , H01L24/14 , H01L2224/14515
摘要： A semiconductor package includes a semiconductor chip having Hall elements built therein, and external terminals arranged on one surface side of the semiconductor chip. A first Hall element and a second Hall element are arranged to be point-symmetrical with respect to a center point of the semiconductor package in a plan view. The first Hall element is at least partially covered by a first external terminal among first external terminals in a plan view, and the second Hall element is at least partially covered by a second external terminal among second external terminals in a plan view. A first region covered by the first external terminal of the first Hall element in a plan view and a second region covered by the second external terminal of the second Hall element in a plan view are point-symmetrical with respect to the center point of the semiconductor package in a plan view.
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公开(公告)号：US20230387108A1
公开(公告)日：2023-11-30
申请号：US18362030
申请日：2023-07-31
发明人： Chung-Te LIN , Wei-Yuan LU , Feng-Cheng YANG
IPC分类号： H01L27/088 , H01L23/522 , H01L23/48 , H01L29/06 , H01L27/06 , H01L29/66 , H01L21/8234 , H10B10/00 , H10B61/00 , H10N59/00
CPC分类号： H01L27/088 , H01L23/5226 , H01L23/481 , H01L29/0653 , H01L27/0688 , H01L29/66545 , H01L28/40 , H01L21/823475 , H01L23/5222 , H10B10/12 , H10B61/00 , H10N59/00 , H01L21/8258
摘要： A method comprises growing an epitaxial layer on a first region of a first wafer while remaining a second region of the first wafer exposed; forming a first dielectric layer over the epitaxial layer and the second region; forming a first transistor on a second wafer; forming a second dielectric layer over the first transistor; bonding the first and second dielectric layers; and forming second and third transistors on the epitaxial layer and on the second region of the first wafer, respectively.
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公开(公告)号：US20240284804A1
公开(公告)日：2024-08-22
申请号：US18642280
申请日：2024-04-22
发明人： Shinji YUASA
IPC分类号： H10N50/85 , B82Y10/00 , B82Y25/00 , G11C11/15 , G11C11/16 , H01F10/13 , H01F10/32 , H10B53/30 , H10B61/00 , H10N50/01 , H10N50/10 , H10N50/80 , H10N59/00
CPC分类号： H10N50/85 , B82Y25/00 , G11C11/15 , G11C11/16 , G11C11/161 , H01F10/132 , H01F10/3254 , H01L28/55 , H10B53/30 , H10B61/00 , H10B61/22 , H10N50/01 , H10N50/10 , H10N50/80 , B82Y10/00 , H10N59/00
摘要： The output voltage of an MRAM is increased by means of an Fe(001)/MgO(001)/Fe(001) MTJ device, which is formed by microfabrication of a sample prepared as follows: A single-crystalline MgO (001) substrate is prepared. An epitaxial Fe(001) lower electrode (a first electrode) is grown on a MgO(001) seed layer at room temperature, followed by annealing under ultrahigh vacuum. A MgO(001) barrier layer is epitaxially formed on the Fe(001) lower electrode (the first electrode) at room temperature, using a MgO electron-beam evaporation. A Fe(001) upper electrode (a second electrode) is then formed on the MgO(001) barrier layer at room temperature. This is successively followed by the deposition of a Co layer on the Fe(001) upper electrode (the second electrode). The Co layer is provided so as to increase the coercive force of the upper electrode in order to realize an antiparallel magnetization alignment.
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公开(公告)号：US12013419B2
公开(公告)日：2024-06-18
申请号：US17871873
申请日：2022-07-22
发明人： Dok Won Lee , Jo Bito , Keith Ryan Green
CPC分类号： G01R15/207 , G01R15/202 , H01L23/49586 , H10N52/00 , H10N52/80 , H10B61/00 , H10N59/00
摘要： In one example, circuitry is formed in a semiconductor die. A magnetic concentrator is formed on a surface of the semiconductor die and over the circuitry. An isolation spacer is placed on a lead frame. The semiconductor die is placed on the isolation spacer, and the magnetic concentrator is aligned to overlap the lead frame. Electrical interconnects are formed between the semiconductor die and the lead frame.
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公开(公告)号：US11844284B2
公开(公告)日：2023-12-12
申请号：US17304991
申请日：2021-06-29
摘要： A method of manufacturing and resultant device are directed to an inverted wide-base double magnetic tunnel junction device having both high-efficiency and high-retention arrays. The method includes a method of manufacturing, on a common stack, a high-efficiency array and a high-retention array for an inverted wide-base double magnetic tunnel junction device. The method comprises, for the high-efficiency array and the high-retention array, forming a first magnetic tunnel junction stack (MTJ2), forming a spin conducting layer on the MTJ2, and forming a second magnetic tunnel junction stack (MTJ1) on the spin conducting layer. The first magnetic tunnel junction stack for the high-retention array has a high-retention critical dimension (CD) (HRCD) that is larger than a high-efficiency CD (HECD) of the first magnetic tunnel junction stack for the high-efficiency array. The second magnetic tunnel junction stack (MTJ1) is shorted for the high-retention array and is not shorted for the high-efficiency array.
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