公开(公告)号：US20240407268A1

公开(公告)日：2024-12-05

申请号：US18804178

申请日：2024-08-14

Applicant: Texas Instruments Incorporated

Inventor： Fuchao Wang ,  Christopher Eric Brannon ,  William David French ,  Dok Won Lee

IPC: H10N50/01 ,  G01R33/00 ,  G01R33/09 ,  H01L21/306 ,  H10N50/10 ,  H10N50/80 ,  H10N59/00

Abstract: Apparatus, and their methods of manufacture, including an integrated circuit device having metallization layers for interconnecting underlying electronic devices. Contacts contact conductors of an uppermost one of the metallization layers. A planarized first dielectric layer covers the contacts and the uppermost one of the metallization layers. An anisotropic magnetoresistive (AMR) stack is on the first dielectric layer between vertically aligned portions of an etch stop layer formed on the first dielectric layer and a second dielectric layer formed on the etch stop layer. Vias extend through the first dielectric layer to electrically connect the AMR stack and the contacts. A chemical-mechanical planarization (CMP) stop layer is on the AMR stack. A third dielectric layer is on the CMP stop layer. A passivation layer contacts the second dielectric layer portions, the third dielectric layer, and each opposing end of the AMR stack and the CMP stop layer.

公开(公告)号：US12069956B2

公开(公告)日：2024-08-20

申请号：US17487877

申请日：2021-09-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Fuchao Wang ,  Christopher Eric Brannon ,  William David French ,  Dok Won Lee

IPC: H10N50/01 ,  G01R33/00 ,  G01R33/09 ,  H01L21/306 ,  H10N50/10 ,  H10N50/80 ,  H10N59/00

CPC classification number: H10N50/01 ,  G01R33/0052 ,  G01R33/096 ,  H01L21/30604 ,  H10N50/10 ,  H10N50/80 ,  H10N59/00

Abstract: Apparatus, and their methods of manufacture, including an integrated circuit device having metallization layers for interconnecting underlying electronic devices. Contacts contact conductors of an uppermost one of the metallization layers. A planarized first dielectric layer covers the contacts and the uppermost one of the metallization layers. An anisotropic magnetoresistive (AMR) stack is on the first dielectric layer between vertically aligned portions of an etch stop layer formed on the first dielectric layer and a second dielectric layer formed on the etch stop layer. Vias extend through the first dielectric layer to electrically connect the AMR stack and the contacts. A chemical-mechanical planarization (CMP) stop layer is on the AMR stack. A third dielectric layer is on the CMP stop layer. A passivation layer contacts the second dielectric layer portions, the third dielectric layer, and each opposing end of the AMR stack and the CMP stop layer.

公开(公告)号：US20230096573A1

公开(公告)日：2023-03-30

申请号：US17487877

申请日：2021-09-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Fuchao Wang ,  Christopher Eric Brannon ,  William David French ,  Dok Won Lee

IPC: H01L43/12 ,  H01L43/02 ,  H01L21/306 ,  G01R33/09

Abstract: Apparatus, and their methods of manufacture, including an integrated circuit device having metallization layers for interconnecting underlying electronic devices. Contacts contact conductors of an uppermost one of the metallization layers. A planarized first dielectric layer covers the contacts and the uppermost one of the metallization layers. An anisotropic magnetoresistive (AMR) stack is on the first dielectric layer between vertically aligned portions of an etch stop layer formed on the first dielectric layer and a second dielectric layer formed on the etch stop layer. Vias extend through the first dielectric layer to electrically connect the AMR stack and the contacts. A chemical-mechanical planarization (CMP) stop layer is on the AMR stack. A third dielectric layer is on the CMP stop layer. A passivation layer contacts the second dielectric layer portions, the third dielectric layer, and each opposing end of the AMR stack and the CMP stop layer.