公开(公告)号：US12069956B2

公开(公告)日：2024-08-20

申请号：US17487877

申请日：2021-09-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Fuchao Wang ,  Christopher Eric Brannon ,  William David French ,  Dok Won Lee

IPC: H10N50/01 ,  G01R33/00 ,  G01R33/09 ,  H01L21/306 ,  H10N50/10 ,  H10N50/80 ,  H10N59/00

CPC classification number: H10N50/01 ,  G01R33/0052 ,  G01R33/096 ,  H01L21/30604 ,  H10N50/10 ,  H10N50/80 ,  H10N59/00

Abstract: Apparatus, and their methods of manufacture, including an integrated circuit device having metallization layers for interconnecting underlying electronic devices. Contacts contact conductors of an uppermost one of the metallization layers. A planarized first dielectric layer covers the contacts and the uppermost one of the metallization layers. An anisotropic magnetoresistive (AMR) stack is on the first dielectric layer between vertically aligned portions of an etch stop layer formed on the first dielectric layer and a second dielectric layer formed on the etch stop layer. Vias extend through the first dielectric layer to electrically connect the AMR stack and the contacts. A chemical-mechanical planarization (CMP) stop layer is on the AMR stack. A third dielectric layer is on the CMP stop layer. A passivation layer contacts the second dielectric layer portions, the third dielectric layer, and each opposing end of the AMR stack and the CMP stop layer.

公开(公告)号：US20240102830A1

公开(公告)日：2024-03-28

申请号：US18147396

申请日：2022-12-28

Applicant: Texas Instruments Incorporated

Inventor： Fuchao Wang ,  William French ,  Ricky A. Jackson ,  Erika Mazotti

IPC: G01D5/16 ,  G01D5/18 ,  G01R33/09

CPC classification number: G01D5/16 ,  G01D5/18 ,  G01R33/096

Abstract: Barrier layers for anisotropic magneto-resistive (AMR) sensors integrated with semiconductor circuits and methods of making the same are described. The AMR sensors includes a NiFe alloy layer disposed over a dielectric layer. The NiFe alloy layer is in contact with a conductive via coupled to the semiconductor circuits in a substrate underneath the AMR sensor. A barrier layer is formed on the dielectric layer to prevent Ni or Fe atoms from diffusing through the dielectric layer toward the semiconductor circuits. Further, a sacrificial layer is used to facilitate forming a planarized surface with ends of the conductive vias exposed without compromising the barrier layer.

公开(公告)号：US20230096573A1

公开(公告)日：2023-03-30

申请号：US17487877

申请日：2021-09-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Fuchao Wang ,  Christopher Eric Brannon ,  William David French ,  Dok Won Lee

IPC: H01L43/12 ,  H01L43/02 ,  H01L21/306 ,  G01R33/09

Abstract: Apparatus, and their methods of manufacture, including an integrated circuit device having metallization layers for interconnecting underlying electronic devices. Contacts contact conductors of an uppermost one of the metallization layers. A planarized first dielectric layer covers the contacts and the uppermost one of the metallization layers. An anisotropic magnetoresistive (AMR) stack is on the first dielectric layer between vertically aligned portions of an etch stop layer formed on the first dielectric layer and a second dielectric layer formed on the etch stop layer. Vias extend through the first dielectric layer to electrically connect the AMR stack and the contacts. A chemical-mechanical planarization (CMP) stop layer is on the AMR stack. A third dielectric layer is on the CMP stop layer. A passivation layer contacts the second dielectric layer portions, the third dielectric layer, and each opposing end of the AMR stack and the CMP stop layer.

公开(公告)号：US20190341181A1

公开(公告)日：2019-11-07

申请号：US16512642

申请日：2019-07-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Fuchao Wang ,  Yousong Zhang ,  Neal Thomas Murphy ,  Brian Zinn ,  Jonathan P. Davis

IPC: H01F10/30 ,  H01F17/00 ,  H01F41/04

Abstract: An integrated magnetic device has a magnetic core which includes layers of the magnetic material located in a trench in a dielectric layer. The magnetic material layers are flat and parallel to a bottom of the trench, and do not extend upward along sides of the trench. The integrated magnetic device is formed by forming layers of the magnetic material over the dielectric layer and extending into the trench. A protective layer is formed over the magnetic material layers. The magnetic material layers are removed from over the dielectric layer, leaving the magnetic material layers and a portion of the protective layer in the trench. The magnetic material layers along sides of the trench are subsequently removed. The magnetic material layers along the bottom of the trench provide the magnetic core.

公开(公告)号：US09842895B2

公开(公告)日：2017-12-12

申请号：US15055959

申请日：2016-02-29

Applicant: Texas Instruments Incorporated

Inventor： Pinghai Hao ,  Fuchao Wang ,  Duofeng Yue

IPC: H01C1/012 ,  H01L49/02 ,  H01C17/06 ,  H01C7/00 ,  H01C17/075

CPC classification number: H01L28/24 ,  H01C7/006 ,  H01C17/06 ,  H01C17/075 ,  Y10T29/435

Abstract: An integrated circuit contains a thin film resistor in which a body of the thin film resistor is disposed over a lower dielectric layer in a system of interconnects in the integrated circuit. Heads of the thin film resistor are disposed over electrodes which are interconnect elements in the lower dielectric layer, which provide electrical connections to a bottom surface of the thin film resistor. Top surfaces of the electrodes are substantially coplanar with a top surface of the lower dielectric layer. A top surface of the thin film resistor is free of electrical connections. An upper dielectric layer is disposed over the thin film resistor.

公开(公告)号：US11443879B2

公开(公告)日：2022-09-13

申请号：US16512642

申请日：2019-07-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Fuchao Wang ,  Yousong Zhang ,  Neal Thomas Murphy ,  Brian Zinn ,  Jonathan P. Davis

IPC: H01F10/00 ,  H01F10/30 ,  H01F17/00 ,  H01F41/04 ,  H01F27/24

Abstract: An integrated magnetic device has a magnetic core which includes layers of the magnetic material located in a trench in a dielectric layer. The magnetic material layers are flat and parallel to a bottom of the trench, and do not extend upward along sides of the trench. The integrated magnetic device is formed by forming layers of the magnetic material over the dielectric layer and extending into the trench. A protective layer is formed over the magnetic material layers. The magnetic material layers are removed from over the dielectric layer, leaving the magnetic material layers and a portion of the protective layer in the trench. The magnetic material layers along sides of the trench are subsequently removed. The magnetic material layers along the bottom of the trench provide the magnetic core.

公开(公告)号：US20180358163A1

公开(公告)日：2018-12-13

申请号：US15618353

申请日：2017-06-09

Applicant: Texas Instruments Incorporated

Inventor： Fuchao Wang ,  Yousong Zhang ,  Neal Thomas Murphy ,  Brian Zinn ,  Jonathan P. Davis

IPC: H01F27/245 ,  H01F41/02 ,  H01F1/147

CPC classification number: H01F10/30 ,  H01F17/0033 ,  H01F41/046

Abstract: An integrated magnetic device has a magnetic core which includes layers of the magnetic material located in a trench in a dielectric layer. The magnetic material layers are flat and parallel to a bottom of the trench, and do not extend upward along sides of the trench. The integrated magnetic device is formed by forming layers of the magnetic material over the dielectric layer and extending into the trench. A protective layer is formed over the magnetic material layers. The magnetic material layers are removed from over the dielectric layer, leaving the magnetic material layers and a portion of the protective layer in the trench. The magnetic material layers along sides of the trench are subsequently removed. The magnetic material layers along the bottom of the trench provide the magnetic core.

公开(公告)号：US10068769B2

公开(公告)日：2018-09-04

申请号：US15379251

申请日：2016-12-14

Applicant: Texas Instruments Incorporated

Inventor： Prakash Dalpatbhai Dev ,  Fuchao Wang ,  Nicholas Andrew Kusek

IPC: H01L21/31 ,  H01L21/225 ,  H01L21/324 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3065

CPC classification number: H01L21/30655 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/26513 ,  H01L21/31111 ,  H01L21/324

Abstract: In a described example method, semiconductor wafer with a backside silicon nitride layer is encapsulated with a diffusion barrier layer prior to a high temperature anneal greater than about 1000 degrees Celsius. After the high temperature anneal the diffusion barrier layer and the backside silicon nitride layers are stripped.

公开(公告)号：US09305688B2

公开(公告)日：2016-04-05

申请号：US14046177

申请日：2013-10-04

Applicant: Texas Instruments Incorporated

Inventor： PingHai Hao ,  Fuchao Wang ,  Duofeng Yue

IPC: H01C1/012 ,  H01C17/06 ,  H01L49/02 ,  H01C7/00 ,  H01C17/075

CPC classification number: H01L28/24 ,  H01C7/006 ,  H01C17/06 ,  H01C17/075 ,  Y10T29/435

Abstract: An integrated circuit contains a thin film resistor in which a body of the thin film resistor is disposed over a lower dielectric layer in a system of interconnects in the integrated circuit. Heads of the thin film resistor are disposed over electrodes which are interconnect elements in the lower dielectric layer, which provide electrical connections to a bottom surface of the thin film resistor. Top surfaces of the electrodes are substantially coplanar with a top surface of the lower dielectric layer. A top surface of the thin film resistor is free of electrical connections. An upper dielectric layer is disposed over the thin film resistor.

Abstract translation: 集成电路包括薄膜电阻器，其中薄膜电阻体的主体设置在集成电路中的互连系统中的下介电层上。 薄膜电阻器的头部设置在电介质上，电极是下电介质层中的互连元件，其提供与薄膜电阻器的底表面的电连接。 电极的顶表面与下介电层的顶表面基本共面。 薄膜电阻的顶表面没有电气连接。 上电介质层设置在薄膜电阻器的上方。

公开(公告)号：US20240407268A1

公开(公告)日：2024-12-05

申请号：US18804178

申请日：2024-08-14

Applicant: Texas Instruments Incorporated

Inventor： Fuchao Wang ,  Christopher Eric Brannon ,  William David French ,  Dok Won Lee

IPC: H10N50/01 ,  G01R33/00 ,  G01R33/09 ,  H01L21/306 ,  H10N50/10 ,  H10N50/80 ,  H10N59/00

Abstract: Apparatus, and their methods of manufacture, including an integrated circuit device having metallization layers for interconnecting underlying electronic devices. Contacts contact conductors of an uppermost one of the metallization layers. A planarized first dielectric layer covers the contacts and the uppermost one of the metallization layers. An anisotropic magnetoresistive (AMR) stack is on the first dielectric layer between vertically aligned portions of an etch stop layer formed on the first dielectric layer and a second dielectric layer formed on the etch stop layer. Vias extend through the first dielectric layer to electrically connect the AMR stack and the contacts. A chemical-mechanical planarization (CMP) stop layer is on the AMR stack. A third dielectric layer is on the CMP stop layer. A passivation layer contacts the second dielectric layer portions, the third dielectric layer, and each opposing end of the AMR stack and the CMP stop layer.