Magnetic memory structures using electric-field controlled interlayer exchange coupling (IEC) for magnetization switching

    公开(公告)号:US10964468B2

    公开(公告)日:2021-03-30

    申请号:US16510343

    申请日:2019-07-12

    摘要: A magnetic memory structure employs electric-field controlled interlayer exchange coupling between a free magnetic layer and a fixed magnetic layer to switch a magnetization direction. The magnetic layers are separated by a spacer layer disposed between two oxide layers. The spacer layer exhibits a large IEC while the oxide layers provide tunnel barriers, forming a quantum-well between the magnetic layers with discrete energy states above the equilibrium Fermi level. When an electric field is applied across the structure, the tunnel barriers become transparent at discrete energy states via a resonant tunneling phenomenon. The wave functions of the two magnets then can interact and interfere to provide a sizable IEC. IEC can control the magnetization direction of the free magnetic layer relative to the magnetization direction of the fixed magnetic layer depending on the sign of the IEC, induced by a magnitude of the applied electric field above a threshold value.

    SUPERLATTICE, FERROIC ORDER THIN FILMS FOR USE AS HIGH/NEGATIVE-K DIELECTRIC

    公开(公告)号:US20240186399A1

    公开(公告)日:2024-06-06

    申请号:US18553602

    申请日:2022-04-05

    IPC分类号: H01L29/51 H01L21/02 H01L29/40

    摘要: Disclosed are HfO2—ZrO2 superlattice heterostructures such as a gate stack (24), stabilized with mixed ferroelectric-antiferroelectric order. directly integrated onto silicon (Si) transistors and scaled down to ˜20 Å. the same gate oxide thickness required for high-performance transistors. The overall equivalent oxide thickness in metal-oxide-semiconductor capacitors is ˜6.5 Å effective SiO2 thickness, which is even smaller than the interfacial SiO2 thickness (8.0-8.5 Å) itself. and the resulting large capacitance cannot be achieved in conventional HfO2-based high-κ dielectric gate stacks without scavenging the interfacial SiO2. which has adverse effects on the electron transport and gate leakage current. Accordingly. the disclosed gate stacks (24), which do not require such scavenging. provide substantially lower leakage current and no mobility degradation and demonstrate that HfO2—ZrO2 multilayers with competing ferroelectric-antiferroelectric order, stabilized in the sub-2 nm thickness regime, provide a path towards advanced gate oxide stacks in electronic devices beyond the conventional HfO2-based high-κ dielectrics.

    FERROELECTRIC FIELD-EFFECT TRANSISTOR WITH HIGH PERMITTIVITY INTERFACIAL LAYER

    公开(公告)号:US20240136437A1

    公开(公告)日:2024-04-25

    申请号:US18546807

    申请日:2022-02-22

    IPC分类号: H01L29/78 H10B51/30

    CPC分类号: H01L29/78391 H10B51/30

    摘要: A ferroelectric field-effect transistor having an endurance exceeding 1012 cycles is disclosed. The ferroelectric field-effect transistor includes a substrate, a source disposed over a first region of the semiconductor substrate, a drain disposed over a second region of the substrate, wherein the second region is spaced apart from the first region. The ferroelectric field-effect transistor includes a channel made of a semiconductor material within a third region of the substrate that is between the first region and the second region. The ferroelectric field-effect transistor further includes a gate stack having an interfacial layer disposed over the channel, wherein the interfacial layer has a permittivity that is greater than 3.9, and a layer of ferroelectric material disposed over the interfacial layer.

    MAGNETIC MEMORY STRUCTURES USING ELECTRIC-FIELD CONTROLLED INTERLAYER EXCHANGE COUPLING (IEC) FOR MAGNETIZATION SWITCHING

    公开(公告)号:US20210012940A1

    公开(公告)日:2021-01-14

    申请号:US16510343

    申请日:2019-07-12

    摘要: A magnetic memory structure employs electric-field controlled interlayer exchange coupling between a free magnetic layer and a fixed magnetic layer to switch a magnetization direction. The magnetic layers are separated by a spacer layer disposed between two oxide layers. The spacer layer exhibits a large IEC while the oxide layers provide tunnel barriers, forming a quantum-well between the magnetic layers with discrete energy states above the equilibrium Fermi level. When an electric field is applied across the structure, the tunnel barriers become transparent at discrete energy states via a resonant tunneling phenomenon. The wave functions of the two magnets then can interact and interfere to provide a sizable IEC. IEC can control the magnetization direction of the free magnetic layer relative to the magnetization direction of the fixed magnetic layer depending on the sign of the IEC, induced by a magnitude of the applied electric field above a threshold value.

    PROBABILISTIC SWITCHING DEVICE
    8.
    发明申请

    公开(公告)号:US20190130954A1

    公开(公告)日:2019-05-02

    申请号:US16170335

    申请日:2018-10-25

    摘要: A two-terminal stochastic switch is disclosed. The switch includes a magnetic tunnel junction (MTJ) stack, an access switch controlled by a first terminal and coupled to the MTJ stack, such that when the access switch is on, electrical current flows from a first source coupled to the MTJ stack, through the MTJ stack, and through the access switch to a second source, and a digital buffer coupled to the MTJ stack and the access switch which is configured to transform an analog signal associated with a voltage division across the MTJ stack and the access switch to a digital signal, output of the digital buffer forming a second terminal.

    FERROELECTRIC FIELD-EFFECT TRANSISTOR WITH HIGH PERMITTIVITY INTERFACIAL LAYER

    公开(公告)号:US20240234574A9

    公开(公告)日:2024-07-11

    申请号:US18546807

    申请日:2022-02-22

    IPC分类号: H01L29/78 H10B51/30

    CPC分类号: H01L29/78391 H10B51/30

    摘要: A ferroelectric field-effect transistor having an endurance exceeding 1012 cycles is disclosed. The ferroelectric field-effect transistor includes a substrate, a source disposed over a first region of the semiconductor substrate, a drain disposed over a second region of the substrate, wherein the second region is spaced apart from the first region. The ferroelectric field-effect transistor includes a channel made of a semiconductor material within a third region of the substrate that is between the first region and the second region. The ferroelectric field-effect transistor further includes a gate stack having an interfacial layer disposed over the channel, wherein the interfacial layer has a permittivity that is greater than 3.9, and a layer of ferroelectric material disposed over the interfacial layer.