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公开(公告)号：US11527406B2
公开(公告)日：2022-12-13
申请号：US16742433
申请日：2020-01-14
发明人： Sheng-Lin Hsieh , I-Chih Chen , Ching-Pei Hsieh , Kuan Jung Chen
IPC分类号： H01L21/027 , H01L21/033 , H01L21/768
摘要： A method of forming a semiconductor device structure is provided. The method includes forming a resist structure over a substrate. The resist structure includes an anti-reflective coating (ARC) layer and a photoresist layer over the ARC layer. The method further includes patterning the photoresist layer to form a trench therein. The method further includes performing a hydrogen plasma treatment to the patterned photoresist layer. The hydrogen plasma treatment is configured to smooth sidewalls of the trench without etching the ARC layer. The method further includes patterning the ARC layer using the patterned photoresist layer as a etch mask.
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公开(公告)号：US10158069B2
公开(公告)日：2018-12-18
申请号：US15817916
申请日：2017-11-20
IPC分类号： H01L45/00
摘要： A manufacture includes a first electrode having an upper surface and a side surface, a resistance variable film over the first electrode, and a second electrode over the resistance variable film. The resistance variable film extends along the upper surface and the side surface of the first electrode. The second electrode has a side surface. A portion of the side surface of the first electrode and a portion of the side surface of the second electrode sandwich a portion of the resistance variable film.
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公开(公告)号：US20160351803A1
公开(公告)日：2016-12-01
申请号：US15237387
申请日：2016-08-15
IPC分类号： H01L45/00
CPC分类号： H01L45/1253 , H01L45/08 , H01L45/122 , H01L45/1233 , H01L45/1246 , H01L45/146 , H01L45/16 , H01L45/1608 , H01L45/1666 , H01L45/1683
摘要： A memory structure includes a first dielectric layer, having a first top surface, over a conductive structure. A first opening in the first dielectric layer exposes an area of the conductive structure, and has an interior sidewall. A first electrode structure, having a first portion and a second portion, is over the exposed area of the conductive structure. The second portion extends upwardly along the interior sidewall. A resistance variable layer is disposed over the first electrode. A second electrode structure, having a third portion and a fourth portion, is over the resistance variable layer. The third portion has a second top surface below the first top surface of the first dielectric layer. The fourth portion extends upwardly along the resistance variable layer. A second opening is defined by the second electrode structure. At least a part of a second dielectric layer is disposed in the second opening.
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公开(公告)号：US12020933B2
公开(公告)日：2024-06-25
申请号：US18054348
申请日：2022-11-10
发明人： Sheng-Lin Hsieh , I-Chih Chen , Ching-Pei Hsieh , Kuan Jung Chen
IPC分类号： H01L21/027 , H01L21/033 , H01L21/768
CPC分类号： H01L21/0276 , H01L21/0332 , H01L21/0337 , H01L21/76816 , H01L21/76819
摘要： A method of forming a semiconductor device structure includes forming a resist structure over a substrate, the resist structure includes an anti-reflective coating (ARC) layer and a photoresist layer over the ARC layer. The method further includes patterning the photoresist layer to form a trench therein. The method further includes performing a hydrogen plasma treatment to the patterned photoresist layer, wherein the hydrogen plasma treatment is configured to smooth sidewalls of the trench, and the hydrogen plasma treatment is performed at a temperature ranging from about 200° C. to about 600° C. The method further includes patterning the ARC layer using the patterned photoresist layer as a etch mask.
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公开(公告)号：US20180090680A1
公开(公告)日：2018-03-29
申请号：US15817916
申请日：2017-11-20
IPC分类号： H01L45/00
CPC分类号： H01L45/1253 , H01L45/08 , H01L45/1226 , H01L45/146 , H01L45/16
摘要： A manufacture includes a first electrode having an upper surface and a side surface, a resistance variable film over the first electrode, and a second electrode over the resistance variable film. The resistance variable film extends along the upper surface and the side surface of the first electrode. The second electrode has a side surface. A portion of the side surface of the first electrode and a portion of the side surface of the second electrode sandwich a portion of the resistance variable film.
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公开(公告)号：US09837606B2
公开(公告)日：2017-12-05
申请号：US15237387
申请日：2016-08-15
CPC分类号： H01L45/1253 , H01L45/08 , H01L45/122 , H01L45/1233 , H01L45/1246 , H01L45/146 , H01L45/16 , H01L45/1608 , H01L45/1666 , H01L45/1683
摘要： A memory structure includes a first dielectric layer, having a first top surface, over a conductive structure. A first opening in the first dielectric layer exposes an area of the conductive structure, and has an interior sidewall. A first electrode structure, having a first portion and a second portion, is over the exposed area of the conductive structure. The second portion extends upwardly along the interior sidewall. A resistance variable layer is disposed over the first electrode. A second electrode structure, having a third portion and a fourth portion, is over the resistance variable layer. The third portion has a second top surface below the first top surface of the first dielectric layer. The fourth portion extends upwardly along the resistance variable layer. A second opening is defined by the second electrode structure. At least a part of a second dielectric layer is disposed in the second opening.
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公开(公告)号：US08872149B1
公开(公告)日：2014-10-28
申请号：US13954430
申请日：2013-07-30
CPC分类号： H01L45/146 , H01L45/04 , H01L45/12 , H01L45/1233 , H01L45/1675
摘要： A memory cell and method includes a first electrode formed in an opening in a first dielectric layer, the first dielectric layer being formed on a substrate including a metal layer, the opening being configured to allow physical contact between the first electrode and the metal layer, the first electrode having a first width W1 and extending a distance beyond a region defined by the opening, a resistive layer formed on the first electrode and having substantially the first width W1, a capping layer, having a second width W2 less than the first width W1, formed on the resistive layer, a second electrode formed on the capping layer and having substantially the second width W2, a first composite spacer region having at least two different dielectric layers formed on the resistive layer between the first width W1 and the second width W2, and a via coupled to the second electrode.
摘要翻译： 存储单元和方法包括形成在第一电介质层的开口中的第一电极，所述第一介电层形成在包括金属层的基板上，所述开口被配置为允许所述第一电极和所述金属层之间的物理接触， 所述第一电极具有第一宽度W1并且延伸超过由所述开口限定的区域的距离;形成在所述第一电极上并且具有基本上第一宽度W1的电阻层，覆盖层，具有小于所述第一宽度的第二宽度W2 W1，形成在电阻层上，形成在覆盖层上并具有基本上第二宽度W2的第二电极，第一复合间隔区，其具有形成在电阻层上的第一宽度W1和第二宽度之间的至少两个不同电介质层 W2和连接到第二电极的通孔。
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公开(公告)号：US11018299B2
公开(公告)日：2021-05-25
申请号：US16713731
申请日：2019-12-13
IPC分类号： H01L45/00
摘要： A manufacture includes a first electrode having an upper surface and a side surface, a resistance variable film over the first electrode, and a second electrode over the resistance variable film. The resistance variable film extends along the upper surface and the side surface of the first electrode. The second electrode has a side surface. A portion of the side surface of the first electrode and a portion of the side surface of the second electrode sandwich a portion of the resistance variable film.
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公开(公告)号：US09466794B2
公开(公告)日：2016-10-11
申请号：US14987621
申请日：2016-01-04
发明人： Chin-Chieh Yang , Wen-Ting Chu , Yu-Wen Liao , Chih-Yang Chang , Hsia-Wei Chen , Kuo-Chi Tu , Ching-Pei Hsieh
IPC分类号： H01L21/20 , H01L21/311 , H01L45/00 , H01L27/24
CPC分类号： H01L45/1608 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/1273 , H01L45/146 , H01L45/16 , H01L45/1675
摘要： The present disclosure provides a resistive random access memory (RRAM) cells and methods of making the same. The RRAM cell includes a transistor and an RRAM structure. The RRAM structure includes a bottom electrode having a via portion and a non-planar portion, a resistive material layer conformally covering the non-planar portion of the bottom electrode; and, a top electrode on the resistive material layer. The via portion of the bottom electrode is embedded in a first RRAM stop layer. The non-planar portion of the bottom electrode has an apex and is centered above the via portion.
摘要翻译： 本公开提供了一种电阻随机存取存储器（RRAM）单元及其制造方法。 RRAM单元包括晶体管和RRAM结构。 RRAM结构包括具有通孔部分和非平面部分的底部电极，保形地覆盖底部电极的非平面部分的电阻材料层; 以及电阻材料层上的顶部电极。 底部电极的通孔部分嵌入第一RRAM停止层。 底部电极的非平面部分具有顶点并且在通孔部分上方居中。
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公开(公告)号：US20160118584A1
公开(公告)日：2016-04-28
申请号：US14987621
申请日：2016-01-04
发明人： Chin-Chieh Yang , Wen-Ting Chu , Yu-Wen Liao , Chih-Yang Chang , Hsia-Wei Chen , Kuo-Chi Tu , Ching-Pei Hsieh
CPC分类号： H01L45/1608 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/1273 , H01L45/146 , H01L45/16 , H01L45/1675
摘要： The present disclosure provides a resistive random access memory (RRAM) cells and methods of making the same. The RRAM cell includes a transistor and an RRAM structure. The RRAM structure includes a bottom electrode having a via portion and a non-planar portion, a resistive material layer conformally covering the non-planar portion of the bottom electrode; and, a top electrode on the resistive material layer. The via portion of the bottom electrode is embedded in a first RRAM stop layer. The non-planar portion of the bottom electrode has an apex and is centered above the via portion.
摘要翻译： 本公开提供了一种电阻随机存取存储器（RRAM）单元及其制造方法。 RRAM单元包括晶体管和RRAM结构。 RRAM结构包括具有通孔部分和非平面部分的底部电极，保形地覆盖底部电极的非平面部分的电阻材料层; 以及电阻材料层上的顶部电极。 底部电极的通孔部分嵌入第一RRAM停止层。 底部电极的非平面部分具有顶点并且在通孔部分上方居中。
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