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公开(公告)号：US09934853B2
公开(公告)日：2018-04-03
申请号：US15425213
申请日：2017-02-06
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chin-Chieh Yang , Chih-Yang Chang , Chang-Sheng Liao , Hsia-Wei Chen , Jen-Sheng Yang , Kuo-Chi Tu , Sheng-Hung Shih , Wen-Ting Chu , Manish Kumar Singh , Chi-Tsai Chen
CPC classification number: G11C13/004 , G11C11/1653 , G11C11/1655 , G11C11/1657 , G11C11/1673 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C2213/79 , G11C2213/82
Abstract: The present disclosure relates to a method and apparatus for performing a read operation of an RRAM cell, which applies a non-zero bias voltage to unselected bit-lines and select-lines to increase a read current window without damaging corresponding access transistors. In some embodiments, the method may be performed by activating a word-line coupled to a row of RRAM cells comprising a selected RRAM device by applying a first read voltage to the word-line. A second read voltage is applied to a bit-line coupled to a first electrode of the selected RRAM device. One or more non-zero bias voltages are applied to bit-lines and select-lines coupled to RRAM cells, within the row of RRAM cells, having unselected RRAM devices.
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Patent Agency Ranking
公开(公告)号：US10796759B2
公开(公告)日：2020-10-06
申请号：US16413937
申请日：2019-05-16
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chin-Chieh Yang , Chih-Yang Chang , Chang-Sheng Liao , Hsia-Wei Chen , Jen-Sheng Yang , Kuo-Chi Tu , Sheng-Hung Shih , Wen-Ting Chu , Manish Kumar Singh , Chi-Tsai Chen
Abstract: The present disclosure, in some embodiments, relates to a method of operating a resistive random access memory (RRAM) array. The method includes applying a word-line voltage to a selected word-line during a read operation. A non-zero voltage is applied to a selected bit-line during the read operation. A first voltage is applied to a selected source-line during the read operation. The first voltage is smaller than a second voltage applied to an unselected source-line during the read operation.
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公开(公告)号：US20190272873A1
公开(公告)日：2019-09-05
申请号：US16413937
申请日：2019-05-16
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chin-Chieh Yang , Chih-Yang Chang , Chang-Sheng Liao , Hsia-Wei Chen , Jen-Sheng Yang , Kuo-Chi Tu , Sheng-Hung Shih , Wen-Ting Chu , Manish Kumar Singh , Chi-Tsai Chen
Abstract: The present disclosure, in some embodiments, relates to a method of operating a resistive random access memory (RRAM) array. The method includes applying a word-line voltage to a selected word-line during a read operation. A non-zero voltage is applied to a selected bit-line during the read operation. A first voltage is applied to a selected source-line during the read operation. The first voltage is smaller than a second voltage applied to an unselected source-line during the read operation.
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公开(公告)号：US10311952B2
公开(公告)日：2019-06-04
申请号：US15937257
申请日：2018-03-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chin-Chieh Yang , Chih-Yang Chang , Chang-Sheng Liao , Hsia-Wei Chen , Jen-Sheng Yang , Kuo-Chi Tu , Sheng-Hung Shih , Wen-Ting Chu , Manish Kumar Singh , Chi-Tsai Chen
Abstract: In some embodiments, the present disclosure relates to a resistive random access memory (RRAM) memory circuit. The memory circuit has a word-line decoder operably coupled to a first RRAM device and a second RRAM device by a word-line. A bit-line decoder is coupled to the first RRAM device by a first bit-line and to the second RRAM device by a second bit-line. A bias element is configured to apply a first non-zero bias voltage to the second bit-line concurrent to the bit-line decoder applying a non-zero voltage to the first bit-line.
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公开(公告)号：US20180218770A1
公开(公告)日：2018-08-02
申请号：US15937257
申请日：2018-03-27
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chin-Chieh Yang , Chih-Yang Chang , Chang-Sheng Liao , Hsia-Wei Chen , Jen-Sheng Yang , Kuo-Chi Tu , Sheng-Hung Shih , Wen-Ting Chu , Manish Kumar Singh , Chi-Tsai Chen
CPC classification number: G11C13/004 , G11C11/1653 , G11C11/1655 , G11C11/1657 , G11C11/1673 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C2213/79 , G11C2213/82
Abstract: In some embodiments, the present disclosure relates to a resistive random access memory (RRAM) memory circuit. The memory circuit has a word-line decoder operably coupled to a first RRAM device and a second RRAM device by a word-line. A bit-line decoder is coupled to the first RRAM device by a first bit-line and to the second RRAM device by a second bit-line. A bias element is configured to apply a first non-zero bias voltage to the second bit-line concurrent to the bit-line decoder applying a non-zero voltage to the first bit-line.
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公开(公告)号：US20170236581A1
公开(公告)日：2017-08-17
申请号：US15425213
申请日：2017-02-06
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chin-Chieh Yang , Chih-Yang Chang , Chang-Sheng Liao , Hsia-Wei Chen , Jen-Sheng Yang , Kuo-Chi Tu , Sheng-Hung Shih , Wen-Ting Chu , Manish Kumar Singh , Chi-Tsai Chen
IPC: G11C13/00
CPC classification number: G11C13/004 , G11C11/1653 , G11C11/1655 , G11C11/1657 , G11C11/1673 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C2213/79 , G11C2213/82
Abstract: The present disclosure relates to a method and apparatus for performing a read operation of an RRAM cell, which applies a non-zero bias voltage to unselected bit-lines and select-lines to increase a read current window without damaging corresponding access transistors. In some embodiments, the method may be performed by activating a word-line coupled to a row of RRAM cells comprising a selected RRAM device by applying a first read voltage to the word-line. A second read voltage is applied to a bit-line coupled to a first electrode of the selected RRAM device. One or more non-zero bias voltages are applied to bit-lines and select-lines coupled to RRAM cells, within the row of RRAM cells, having unselected RRAM devices.
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