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    Memory circuit and formation method thereof
    2.
    发明授权
    Memory circuit and formation method thereof 有权

    公开(公告)号：US10461126B2

    公开(公告)日：2019-10-29

    申请号：US15678557

    申请日：2017-08-16

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chun-Yang Tsai ,  Kuo-Ching Huang ,  Tong-Chern Ong

    IPC: H01L29/788 ,  H01L21/336 ,  H01L27/24 ,  G11C13/00 ,  H01L45/00 ,  G11C11/16

    Abstract: The present disclosure relates to a memory circuit having a shared control device for access to target and complementary memory devices for improved differential sensing. The memory circuit has a control device arranged within a substrate and having a first terminal coupled to a source-line, a second terminal coupled to a word-line, and a third terminal. A first memory device has a first lower electrode separated from a first upper electrode by a first data storage layer. The first upper electrode is coupled to the third terminal and the first lower electrode is coupled to a first bit-line. A second memory device has a second lower electrode separated from a second upper electrode by a second data storage layer. The second upper electrode is coupled to the second bit-line and the second lower electrode is coupled to the third terminal.

    RRAM-BASED MONOTONIC COUNTER
    4.
    发明申请
    RRAM-BASED MONOTONIC COUNTER 审中-公开

    公开(公告)号：US20200051631A1

    公开(公告)日：2020-02-13

    申请号：US16654748

    申请日：2019-10-16

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shih-Lien Linus LU ,  Yu-Der Chih ,  Chung-Cheng Chou ,  Tong-Chern Ong

    IPC: G11C13/00 ,  G06F21/64 ,  G06F12/14 ,  G06F21/79 ,  G06F12/02

    Abstract: A circuit includes a memory array having a plurality of memory cells; a control logic circuit, coupled to the memory array, and configured to use a first voltage signal to cause a first memory cell of the plurality of memory cells to transition from a first resistance state to a second resistance state; a counter circuit, coupled to the control logic circuit, and configured to increment a count by one in response to the first memory cell's transition from the first to the second resistance state; and an encryption circuit, coupled to the counter circuit, configured to generate an encrypted value using an updated count provided by the counter circuit.

    RRAM-based monotonic counter
    5.
    发明授权
    RRAM-based monotonic counter 有权

    公开(公告)号：US10482958B2

    公开(公告)日：2019-11-19

    申请号：US15898119

    申请日：2018-02-15

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shih-Lien Linus Lu ,  Yu-Der Chih ,  Chung-Cheng Chou ,  Tong-Chern Ong

    IPC: G11C13/00 ,  G06F21/64 ,  G06F12/14 ,  G06F21/79 ,  G11C7/24

    Abstract: A circuit includes a memory array having a plurality of memory cells; a control logic circuit, coupled to the memory array, and configured to use a first voltage signal to cause a first memory cell of the plurality of memory cells to transition from a first resistance state to a second resistance state, and a second voltage signal to cause the first memory cell to transition from the second resistance state to a third resistance state; and a counter circuit, coupled to the control logic circuit, and configured to increment a count by one in response to the first memory cell's transition from the first to the second resistance state, and again increment the count by one in response to the first memory cell's transition from the second to the third resistance state.

    Electrode structure to improve RRAM performance
    6.
    发明授权
    Electrode structure to improve RRAM performance 有权

    公开(公告)号：US11329221B2

    公开(公告)日：2022-05-10

    申请号：US16693946

    申请日：2019-11-25

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Wen-Ting Chu ,  Tong-Chern Ong ,  Ying-Lang Wang

    IPC: H01L45/00 ,  H01L27/24

    Abstract: The present disclosure, in some embodiments, relates to a method of forming a resistive random access memory (RRAM) device. The method includes forming one or more bottom electrode films over a lower interconnect layer within a lower inter-level dielectric layer. A data storage film having a variable resistance is formed above the one or more bottom electrode films. A lower top electrode film including a metal is over the data storage film, one or more oxygen barrier films are over the lower top electrode film, and an upper top electrode film including a metal nitride is formed over the one or more oxygen barrier films. The one or more oxygen barrier films include one or more of a metal oxide film and a metal oxynitride film. The upper top electrode film is formed to be completely confined over a top surface of the one or more oxygen barrier films.

    MEMORY CIRCUIT AND FORMATION METHOD THEREOF
    7.
    发明申请
    MEMORY CIRCUIT AND FORMATION METHOD THEREOF 审中-公开

    公开(公告)号：US20190058007A1

    公开(公告)日：2019-02-21

    申请号：US15678557

    申请日：2017-08-16

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chun-Yang Tsai ,  Kuo-Ching Huang ,  Tong-Chern Ong

    IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

    Abstract: The present disclosure relates to a memory circuit having a shared control device for access to target and complementary memory devices for improved differential sensing. The memory circuit has a control device arranged within a substrate and having a first terminal coupled to a source-line, a second terminal coupled to a word-line, and a third terminal. A first memory device has a first lower electrode separated from a first upper electrode by a first data storage layer. The first upper electrode is coupled to the third terminal and the first lower electrode is coupled to a first bit-line. A second memory device has a second lower electrode separated from a second upper electrode by a second data storage layer. The second upper electrode is coupled to the second bit-line and the second lower electrode is coupled to the third terminal.

    RRAM retention by depositing Ti capping layer before HK HfO
    9.
    发明授权
    RRAM retention by depositing Ti capping layer before HK HfO 有权
    在HKHOO之前沉积Ti覆盖层的RRAM保留

    公开(公告)号：US09385316B2

    公开(公告)日：2016-07-05

    申请号：US14196416

    申请日：2014-03-04

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Wen Liao ,  Wen-Ting Chu ,  Tong-Chern Ong

    IPC: H01L45/00 ,  H01L27/24

    CPC classification number: H01L45/146 ,  H01L27/2436 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1675

    Abstract: The present disclosure relates to a resistance random access memory (RRAM) device architecture where a Ti metal capping layer is deposited before the deposition of the HK HfO resistance switching layer. Here, the capping layer is below the HK HfO layer, and hence no damage will occur during the top RRAM electrode etching. The outer sidewalls of the capping layer are substantially aligned with the sidewalls of the HfO layer and hence any damage that may occur during future etching steps will happen at the outer side walls of the capping layer that are positioned away from the oxygen vacancy filament (conductive filament) in the HK HfO layer. Thus the architecture in the present disclosure, improves data retention.

    Abstract translation: 本公开涉及在沉积HK HfO电阻切换层之前沉积Ti金属覆盖层的电阻随机存取存储器（RRAM）器件结构。 这里，覆盖层在HK HfO层之下，因此在顶部RRAM电极蚀刻期间不会发生损坏。 覆盖层的外侧壁基本上与HfO层的侧壁对准，因此在将来的蚀刻步骤期间可能发生的任何损坏将发生在封盖层的远离氧空位丝的外侧壁（导电 灯丝）在HK HfO层。 因此，本公开的架构改善了数据保留。

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