公开(公告)号：US11489107B2

公开(公告)日：2022-11-01

申请号：US17009905

申请日：2020-09-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Che Ku ,  Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Tsun Chung Tu ,  Jiunyu Tsai ,  Sheng-Huang Huang

IPC: H01L43/02 ,  H01F10/32 ,  H01L27/22 ,  H01L43/12 ,  H01L23/528 ,  H01L21/768 ,  H01F41/34 ,  H01L23/522 ,  G11C11/16

Abstract: The present disclosure relates to a method of forming an integrated chip. The method includes forming an ILD layer over a memory device over a substrate. A hard mask structure is formed over the ILD layer and a patterning structure is formed over the hard mask structure. The hard mask structure has sidewalls defining a first opening directly over the memory device and centered along a first line perpendicular to an upper surface of the substrate. The patterning structure has sidewalls defining a second opening directly over the memory device and centered along a second line parallel to the first line. The second line is laterally offset from the first line by a non-zero distance. The ILD layer is etched below an overlap of the first and second openings to define a top electrode via hole. The top electrode via hole is with a conductive material.

公开(公告)号：US11189659B2

公开(公告)日：2021-11-30

申请号：US16423276

申请日：2019-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Jiunyu Tsai ,  Sheng-Huang Huang

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: Some embodiments relate to an integrated circuit including a magnetoresistive random-access memory (MRAM) cell. The integrated circuit includes a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes metal layers that are stacked over one another with dielectric layers disposed between. The metal layers include a lower metal layer and an upper metal layer disposed over the lower metal layer. A bottom electrode is disposed over and in electrical contact with the lower metal layer. A magnetic tunneling junction (MTJ) is disposed over an upper surface of bottom electrode. A top electrode is disposed over an upper surface of the MTJ. A sidewall spacer surrounds an outer periphery of the top electrode. Less than an entirety of a top electrode surface is in direct electrical contact with a metal via connected to the upper metal layer.

公开(公告)号：US11075335B2

公开(公告)日：2021-07-27

申请号：US16408815

申请日：2019-05-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Chen-Pin Hsu ,  Hung Cho Wang ,  Wen-Chun You ,  Sheng-Chang Chen ,  Tsun Chung Tu ,  Jiunyu Tsai ,  Sheng-Huang Huang

IPC: H01L21/768 ,  H01L43/12 ,  H01L43/02 ,  H01F10/32 ,  H01L27/22 ,  H01L23/528 ,  H01F41/32 ,  H01L23/522

Abstract: Some embodiments relate to a method for manufacturing a memory device. The method includes forming a first masking layer disposed over a dielectric layer, the first masking layer exhibiting sidewalls defining an opening disposed above a magnetoresistive random-access memory (MRAM) cell located in an embedded memory region. A first etch is performed to form a first via opening within the dielectric layer above the MRAM cell. A top electrode via layer formed over the MRAM cell and the dielectric layer. A first planarization process performed on the top electrode via layer to remove part of the top electrode via layer and define a top electrode via having a substantially flat top surface.

公开(公告)号：US20210134668A1

公开(公告)日：2021-05-06

申请号：US17007260

申请日：2020-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Huang Huang ,  Chung-Chiang Min ,  Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Sheng-Chang Chen

IPC: H01L21/768 ,  G11C5/06 ,  G11C11/16 ,  H01L21/3213

Abstract: The present disclosure relates to a method of forming an integrated chip. The method includes forming a memory device over a substrate and forming an etch stop layer over the memory device. An inter-level dielectric (ILD) layer is formed over the etch stop layer and laterally surrounding the memory device. One or more patterning process are performed to define a first trench extending from a top of the ILD layer to expose an upper surface of the etch stop layer. A removal process is performed to remove an exposed part of the etch stop layer. A conductive material is formed within the interconnect trench after performing the removal process.

公开(公告)号：US10727274B2

公开(公告)日：2020-07-28

申请号：US16412714

申请日：2019-05-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chang Chen ,  Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Sheng-Huang Huang

IPC: H01L27/22 ,  H01L43/10 ,  H01L23/52 ,  H01L21/768 ,  H01L23/532 ,  H01L43/02 ,  H01F10/32 ,  H01L23/522 ,  H01L23/528 ,  H01L43/12 ,  H01F41/32

Abstract: Some embodiments relate to a memory device. The memory device includes a first magnetoresistive random-access memory (MRAM) cell disposed on a substrate, and a second MRAM cell disposed on the substrate. An inter-level dielectric (ILD) layer is disposed over the substrate. The ILD layer comprises sidewalls defining a trough between the first and second MRAM cells. A dielectric layer disposed over the ILD layer. The dielectric layer completely fills the trough.

公开(公告)号：US11569443B2

公开(公告)日：2023-01-31

申请号：US16935139

申请日：2020-07-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Harry-Hak-Lay Chuang ,  Sheng-Huang Huang ,  Hung-Cho Wang

IPC: H01L43/12 ,  H01L43/02 ,  H01L27/22

Abstract: A method for fabricating the semiconductor device is provided. The method includes depositing a first dielectric layer; forming a first memory cell over the first dielectric layer; depositing a second dielectric layer over the first memory cell; and forming a second memory cell over the second dielectric layer. Forming the first memory cell includes depositing a first resistance switching layer over the first dielectric layer and performing a first physical etching process to pattern the first resistance switching layer into a first resistance switching element. Forming the second memory cell includes depositing a second resistance switching layer over the second dielectric layer and performing a chemical etching process to pattern the second resistance switching layer into a second resistance switching element.

公开(公告)号：US11437433B2

公开(公告)日：2022-09-06

申请号：US16930481

申请日：2020-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chang Chen ,  Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Sheng-Huang Huang

IPC: H01L27/22 ,  H01F10/32 ,  H01F41/32 ,  H01L21/768 ,  H01L43/12 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L43/02

Abstract: Some embodiments relate to a method for forming a memory device. The method includes forming a first memory cell over a substrate and forming a second memory cell over the substrate. Further, an inter-level dielectric (ILD) layer is formed over the substrate such that the ILD layer comprises sidewalls defining a first trough between the first memory cell and the second memory cell. In addition, a first dielectric layer is formed over the ILD layer and within the first trough.

公开(公告)号：US20200350365A1

公开(公告)日：2020-11-05

申请号：US16930481

申请日：2020-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chang Chen ,  Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Sheng-Huang Huang

IPC: H01L27/22 ,  H01F10/32 ,  H01F41/32 ,  H01L21/768 ,  H01L43/12 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L43/02

Abstract: Some embodiments relate to a method for forming a memory device. The method includes forming a first memory cell over a substrate and forming a second memory cell over the substrate. Further, an inter-level dielectric (ILD) layer is formed over the substrate such that the ILD layer comprises sidewalls defining a first trough between the first memory cell and the second memory cell. In addition, a first dielectric layer is formed over the ILD layer and within the first trough.

公开(公告)号：US10790439B2

公开(公告)日：2020-09-29

申请号：US16416555

申请日：2019-05-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Che Ku ,  Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Tsun Chung Tu ,  Jiunyu Tsai ,  Sheng-Huang Huang

IPC: H01L43/02 ,  H01F10/32 ,  H01L27/22 ,  H01L43/12 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01F41/34 ,  G11C11/16

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a magnetoresistive random access memory (MRAM) device surrounded by a dielectric structure disposed over a substrate. The MRAM device includes a magnetic tunnel junction disposed between a bottom electrode and a top electrode. A bottom electrode via couples the bottom electrode to a lower interconnect wire. A top electrode via couples the top electrode to an upper interconnect wire. A bottom surface of the top electrode via has a first width that is smaller than a second width of a bottom surface of the bottom electrode via.

公开(公告)号：US20200098982A1

公开(公告)日：2020-03-26

申请号：US16408815

申请日：2019-05-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Chen-Pin Hsu ,  Hung Cho Wang ,  Wen-Chun You ,  Sheng-Chang Chen ,  Tsun Chung Tu ,  Jiunyu Tsai ,  Sheng-Huang Huang

IPC: H01L43/12 ,  H01L43/02 ,  H01F10/32 ,  H01L27/22 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01F41/32

Abstract: Some embodiments relate to a method for manufacturing a memory device. The method includes forming a first masking layer disposed over a dielectric layer, the first masking layer exhibiting sidewalls defining an opening disposed above a magnetoresistive random-access memory (MRAM) cell located in an embedded memory region. A first etch is performed to form a first via opening within the dielectric layer above the MRAM cell. A top electrode via layer formed over the MRAM cell and the dielectric layer. A first planarization process performed on the top electrode via layer to remove part of the top electrode via layer and define a top electrode via having a substantially flat top surface.