公开(公告)号：US11551736B2

公开(公告)日：2023-01-10

申请号：US16943990

申请日：2020-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Harry-Hak-Lay Chuang ,  Sheng-Huang Huang ,  Hung-Cho Wang ,  Sheng-Chang Chen

IPC: G11C11/16 ,  H01L27/22 ,  G11C5/02 ,  H01L43/02 ,  G11C5/06 ,  H01L43/12

Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a first memory cell and a second memory cell over a substrate, wherein each of the first and second memory cells comprises a bottom electrode, a resistance switching element over the bottom electrode, and a top electrode over the resistance switching element; depositing a first dielectric layer over the first and second memory cells, such that the first dielectric layer has a void between the first and second memory cells; depositing a second dielectric layer over the first dielectric layer; and forming a first conductive feature and a second conductive feature in the first and second dielectric layers and respectively connected with the top electrode of the first memory cell and the top electrode of the second memory cell.

公开(公告)号：US11380580B2

公开(公告)日：2022-07-05

申请号：US17007260

申请日：2020-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Huang Huang ,  Chung-Chiang Min ,  Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Sheng-Chang Chen

IPC: H01L21/768 ,  G11C5/06 ,  H01L21/3213 ,  G11C11/16

Abstract: The present disclosure relates to a method of forming an integrated chip. The method includes forming a memory device over a substrate and forming an etch stop layer over the memory device. An inter-level dielectric (ILD) layer is formed over the etch stop layer and laterally surrounding the memory device. One or more patterning process are performed to define a first trench extending from a top of the ILD layer to expose an upper surface of the etch stop layer. A removal process is performed to remove an exposed part of the etch stop layer. A conductive material is formed within the interconnect trench after performing the removal process.

公开(公告)号：US20200127047A1

公开(公告)日：2020-04-23

申请号：US16412714

申请日：2019-05-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chang Chen ,  Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Sheng-Huang Huang

IPC: H01L27/22 ,  H01L43/02 ,  H01F10/32 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L43/12 ,  H01F41/32 ,  H01L21/768

Abstract: Some embodiments relate to a memory device. The memory device includes a first magnetoresistive random-access memory (MRAM) cell disposed on a substrate, and a second MRAM cell disposed on the substrate. An inter-level dielectric (ILD) layer is disposed over the substrate. The ILD layer comprises sidewalls defining a trough between the first and second MRAM cells. A dielectric layer disposed over the ILD layer. The dielectric layer completely fills the trough.

公开(公告)号：US12223989B2

公开(公告)日：2025-02-11

申请号：US18151994

申请日：2023-01-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Harry-Hak-Lay Chuang ,  Sheng-Huang Huang ,  Hung-Cho Wang ,  Sheng-Chang Chen

IPC: G11C11/16 ,  G11C5/02 ,  G11C5/06 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80

Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a first memory cell and a second memory cell over a substrate, wherein each of the first and second memory cells comprises a bottom electrode, a resistance switching element over the bottom electrode, and a top electrode over the resistance switching element; depositing a first dielectric layer over the first and second memory cells, such that the first dielectric layer has a void between the first and second memory cells; depositing a second dielectric layer over the first dielectric layer; and forming a first conductive feature and a second conductive feature in the first and second dielectric layers and respectively connected with the top electrode of the first memory cell and the top electrode of the second memory cell.

公开(公告)号：US11469269B2

公开(公告)日：2022-10-11

申请号：US16930499

申请日：2020-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chang Chen ,  Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Sheng-Huang Huang

IPC: H01L27/22 ,  H01L43/02 ,  H01F10/32 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L43/12 ,  H01F41/32 ,  H01L23/532

Abstract: Some embodiments relate to an integrated chip. The integrated chip includes a first memory cell overlying a substrate and a second memory cell overlying the substrate. A dielectric structure overlies the substrate. A trench extends into the dielectric structure and is spaced laterally between the first memory cell and the second memory cell. A dielectric layer is disposed within the trench.

公开(公告)号：US20200350366A1

公开(公告)日：2020-11-05

申请号：US16930499

申请日：2020-07-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chang Chen ,  Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Sheng-Huang Huang

IPC: H01L27/22 ,  H01L43/02 ,  H01F10/32 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L43/12 ,  H01F41/32 ,  H01L23/532

Abstract: Some embodiments relate to an integrated chip. The integrated chip includes a first memory cell overlying a substrate and a second memory cell overlying the substrate. A dielectric structure overlies the substrate. A trench extends into the dielectric structure and is spaced laterally between the first memory cell and the second memory cell. A dielectric layer is disposed within the trench.

公开(公告)号：US11322543B2

公开(公告)日：2022-05-03

申请号：US16884353

申请日：2020-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Sheng-Chang Chen ,  Sheng-Huang Huang

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/12

Abstract: Various embodiments of the present disclosure are directed towards a memory device including a protective sidewall spacer layer that laterally encloses a memory cell. An upper inter-level dielectric (ILD) layer overlying a substrate. The memory cell is disposed with the upper ILD layer. The memory cell includes a top electrode, a bottom electrode, and a magnetic tunnel junction (MTJ) structure disposed between the top and bottom electrodes. A sidewall spacer structure laterally surrounds the memory cell. The sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and the protective sidewall spacer layer. The first and second sidewall spacer layers comprise a first material and the protective sidewall spacer layer comprises a second material different from the first material. A conductive wire overlying the first memory cell. The conductive wire contacts the top electrode and the protective sidewall spacer layer.

公开(公告)号：US20210375987A1

公开(公告)日：2021-12-02

申请号：US16884353

申请日：2020-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Sheng-Chang Chen ,  Sheng-Huang Huang

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/12

Abstract: Various embodiments of the present disclosure are directed towards a memory device including a protective sidewall spacer layer that laterally encloses a memory cell. An upper inter-level dielectric (ILD) layer overlying a substrate. The memory cell is disposed with the upper ILD layer. The memory cell includes a top electrode, a bottom electrode, and a magnetic tunnel junction (MTJ) structure disposed between the top and bottom electrodes. A sidewall spacer structure laterally surrounds the memory cell. The sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and the protective sidewall spacer layer. The first and second sidewall spacer layers comprise a first material and the protective sidewall spacer layer comprises a second material different from the first material. A conductive wire overlying the first memory cell. The conductive wire contacts the top electrode and the protective sidewall spacer layer.

公开(公告)号：US11075335B2

公开(公告)日：2021-07-27

申请号：US16408815

申请日：2019-05-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Chen-Pin Hsu ,  Hung Cho Wang ,  Wen-Chun You ,  Sheng-Chang Chen ,  Tsun Chung Tu ,  Jiunyu Tsai ,  Sheng-Huang Huang

IPC: H01L21/768 ,  H01L43/12 ,  H01L43/02 ,  H01F10/32 ,  H01L27/22 ,  H01L23/528 ,  H01F41/32 ,  H01L23/522

Abstract: Some embodiments relate to a method for manufacturing a memory device. The method includes forming a first masking layer disposed over a dielectric layer, the first masking layer exhibiting sidewalls defining an opening disposed above a magnetoresistive random-access memory (MRAM) cell located in an embedded memory region. A first etch is performed to form a first via opening within the dielectric layer above the MRAM cell. A top electrode via layer formed over the MRAM cell and the dielectric layer. A first planarization process performed on the top electrode via layer to remove part of the top electrode via layer and define a top electrode via having a substantially flat top surface.

公开(公告)号：US20210134668A1

公开(公告)日：2021-05-06

申请号：US17007260

申请日：2020-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Huang Huang ,  Chung-Chiang Min ,  Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Sheng-Chang Chen

IPC: H01L21/768 ,  G11C5/06 ,  G11C11/16 ,  H01L21/3213

Abstract: The present disclosure relates to a method of forming an integrated chip. The method includes forming a memory device over a substrate and forming an etch stop layer over the memory device. An inter-level dielectric (ILD) layer is formed over the etch stop layer and laterally surrounding the memory device. One or more patterning process are performed to define a first trench extending from a top of the ILD layer to expose an upper surface of the etch stop layer. A removal process is performed to remove an exposed part of the etch stop layer. A conductive material is formed within the interconnect trench after performing the removal process.