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公开(公告)号：US20230113903A1
公开(公告)日：2023-04-13
申请号：US18080696
申请日：2022-12-13
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yu-Der CHIH , Chung-Cheng Chou , Wen-Ting Chu
IPC: G11C13/00
Abstract: A memory architecture includes: a plurality of cell arrays each of which comprises a plurality of bit cells, wherein each of bit cells of the plurality of cell arrays uses a respective variable resistance dielectric layer to transition between first and second logic states; and a control logic circuit, coupled to the plurality of cell arrays, and configured to cause a first information bit to be written into respective bit cells of a pair of cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, wherein the respective variable resistance dielectric layers are formed by using a same recipe of deposition equipment and have different diameters.
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公开(公告)号：US11557344B2
公开(公告)日：2023-01-17
申请号：US17330248
申请日：2021-05-25
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yu-Der Chih , Chung-Cheng Chou , Wen-Ting Chu
Abstract: A memory architecture includes: a plurality of cell arrays each of which comprises a plurality of bit cells, wherein each of bit cells of the plurality of cell arrays uses a respective variable resistance dielectric layer to transition between first and second logic states; and a control logic circuit, coupled to the plurality of cell arrays, and configured to cause a first information bit to be written into respective bit cells of a pair of cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, wherein the respective variable resistance dielectric layers are formed by using a same recipe of deposition equipment and have different diameters.
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公开(公告)号：US10916305B2
公开(公告)日：2021-02-09
申请号：US16654748
申请日：2019-10-16
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shih-Lien Linus Lu , Yu-Der Chih , Chung-Cheng Chou , Tong-Chern Ong
Abstract: A circuit includes a memory array having a plurality of memory cells; a control logic circuit, coupled to the memory array, and configured to use a first voltage signal to cause a first memory cell of the plurality of memory cells to transition from a first resistance state to a second resistance state; a counter circuit, coupled to the control logic circuit, and configured to increment a count by one in response to the first memory cell's transition from the first to the second resistance state; and an encryption circuit, coupled to the counter circuit, configured to generate an encrypted value using an updated count provided by the counter circuit.
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4.发明授权公开(公告)号：US10726916B2
公开(公告)日：2020-07-28
申请号：US16105527
申请日：2018-08-20
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Chung-Cheng Chou
Abstract: A device is disclosed that includes a driver and a plurality of resistive memory cells each being electrically connected to the driver through a first line. The driver has a variable resistance corresponding to various locations of a conducted resistive memory cell, relative to the driver, in the plurality of resistive memory cells.
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公开(公告)号：US10288494B2
公开(公告)日：2019-05-14
申请号：US15591976
申请日：2017-05-10
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shih-Lien Linus Lu , Chia-Fu Lee , Yi-Chun Shih , Chung-Cheng Chou , Yu-Der Chih
Abstract: A thermometer circuit configured to estimate a monitored temperature is disclosed. The circuit includes an adjustable resistor presenting a first resistance value that is temperature-independent and a second resistance value that is temperature-dependent, wherein a first current signal is conducted across the resistor when it presents the first resistance value and a second current signal is conducted across the resistor when it presents the second resistance value; a plurality of gated conductors coupled to the resistor; and a control circuit, coupled to the resistor and the plurality of gated conductors, and configured to selectively deactivate at least one of the plurality of gated conductors to compare the first and second current signals to estimate the monitored temperature.
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Patent Agency Ranking
6.发明授权公开(公告)号：US10062434B2
公开(公告)日：2018-08-28
申请号：US15415788
申请日：2017-01-25
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Chung-Cheng Chou
CPC classification number: G11C13/004 , G11C8/00 , G11C11/1653 , G11C11/1673 , G11C11/1675 , G11C13/0007 , G11C13/0023 , G11C13/0033 , G11C13/0069 , G11C2013/0054 , G11C2213/79 , G11C2213/82
Abstract: A device is disclosed that includes a driver, a sinker and a memory column. The memory column includes a plurality of resistive memory cells each being electrically connected between the driver and the sinker through a first line and a second line. When one of the resistive memory cells is conducted, at least one of the driver and the sinker is configured to be controlled to have a resistance depending on a row location of the conducted resistive memory cell in the memory column.
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公开(公告)号：US09620209B2
公开(公告)日：2017-04-11
申请号：US15238167
申请日：2016-08-16
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Yi-Chun Shih , Chung-Cheng Chou , Po-Hao Lee
CPC classification number: G11C13/0069 , G11C13/0026 , G11C13/0038 , G11C13/0064 , G11C2013/0054 , G11C2013/0066 , G11C2213/79
Abstract: Circuits and methods for limiting cell current or throttling write operation, or both, in resistive random access memory (RRAM or ReRAM) cells are provided. An RRAM cell can include a select transistor and a programmable resistor that can change between a relatively high resistance and a relatively low resistance. The present circuits and methods can reduce or inhibit excess current from being applied to the programmable resistor, which potentially can regulate the resistance of the programmable resistor so as to reduce or inhibit decreases in the resistance of that resistor below the relatively low resistance. Such regulation potentially can improve reliability of the RRAM cell. Additionally, or alternatively, the present circuits and methods can throttle a write operation in an RRAM cell, e.g., can disable current flow through the RRAM cell based on the programmable resistor reaching a pre-defined target resistance, such as the relatively low resistance.
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8.发明授权公开(公告)号：US09082496B2
公开(公告)日：2015-07-14
申请号：US13761545
申请日：2013-02-07
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： PoHao Lee , Chung-Cheng Chou
CPC classification number: G11C11/1675 , G11C11/1659 , G11C11/1677 , G11C11/1693 , G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C2013/0054 , G11C2013/0066 , G11C2213/79
Abstract: A bit line, which is coupled to a resistive element of a memory cell is set to a first voltage level. The memory cell may be an MRAM cell or an RRAM cell. The resistive element is configured to have a first resistance in a first state of the memory cell and a second resistance in a second state of the memory cell. A source line, which is selectively coupled to the memory cell by an access transistor, is set to a second voltage level. A word line signal is asserted to apply a first bias voltage across the resistive element. The applied first bias voltage initiates a write operation at the memory cell. The word line signal is deasserted after a variable time duration based on a detection, during the write operation, of a current through the resistive element.
Abstract translation: 耦合到存储器单元的电阻元件的位线被设置为第一电压电平。 存储器单元可以是MRAM单元或RRAM单元。 电阻元件被配置为在存储单元的第一状态下具有第一电阻，并且在存储单元的第二状态下具有第二电阻。 通过存取晶体管选择性地耦合到存储单元的源极线被设置为第二电压电平。 字线信号被断言以在电阻元件上施加第一偏置电压。 所施加的第一偏置电压在存储器单元处启动写入操作。 基于在写入操作期间通过电阻元件的电流的检测，字线信号在可变持续时间后被断言。
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公开(公告)号：US10762960B2
公开(公告)日：2020-09-01
申请号：US16158498
申请日：2018-10-12
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yu-Der Chih , Chung-Cheng Chou , Wen-Ting Chu
Abstract: A memory architecture includes: a plurality of cell arrays each of which comprises a plurality of bit cells, wherein each of bit cells of the plurality of cell arrays uses a respective variable resistance dielectric layer to transition between first and second logic states; and a control logic circuit, coupled to the plurality of cell arrays, and configured to cause a first information bit to be written into respective bit cells of a pair of cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, wherein the respective variable resistance dielectric layers are formed by using a same recipe of deposition equipment and have different diameters.
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公开(公告)号：US20200051631A1
公开(公告)日：2020-02-13
申请号：US16654748
申请日：2019-10-16
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shih-Lien Linus LU , Yu-Der Chih , Chung-Cheng Chou , Tong-Chern Ong
Abstract: A circuit includes a memory array having a plurality of memory cells; a control logic circuit, coupled to the memory array, and configured to use a first voltage signal to cause a first memory cell of the plurality of memory cells to transition from a first resistance state to a second resistance state; a counter circuit, coupled to the control logic circuit, and configured to increment a count by one in response to the first memory cell's transition from the first to the second resistance state; and an encryption circuit, coupled to the counter circuit, configured to generate an encrypted value using an updated count provided by the counter circuit.
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