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公开(公告)号：US12205017B2
公开(公告)日：2025-01-21
申请号：US18231769
申请日：2023-08-08
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Win-San Khwa , Yu-Der Chih , Yi-Chun Shih , Chien-Yin Liu
Abstract: Disclosed is a methods and apparatus which can improve defect tolerability of a hardware-based neural network. In one embodiment, a method for performing a calculation of values on first neurons of a first layer in a neural network, includes: receiving a first pattern of a memory cell array; determining a second pattern of the memory cell array according to a third pattern; determining at least one pair of columns of the memory cell array according to the first pattern and the second pattern; switching input data of two columns of each of the at least one pair of columns of the memory cell array; and switching output data of the two columns in each of the at least one pair of columns of the memory cell array so as to determine the values on the first neurons of the first layer.
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公开(公告)号：US20230393598A1
公开(公告)日：2023-12-07
申请号：US18232772
申请日：2023-08-10
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yen-An CHANG , Chia-Fu Lee , Yu-Der Chih , Yi-Chun Shih
IPC: G05F1/56
CPC classification number: G05F1/56
Abstract: A voltage regulation circuit includes a voltage regulator that is configured to provide a stable output voltage based on an input voltage; and a control circuit, coupled to the voltage regulator, and configured to provide an injection current to maintain the stable output voltage in response to an enable signal provided at an input of the control circuit transitioning to a predetermined state and cease providing the injection current when the control circuit detects that a voltage level of the output voltage is higher than a pre-defined voltage level.
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公开(公告)号：US11461623B2
公开(公告)日：2022-10-04
申请号：US16542049
申请日：2019-08-15
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Win-San Khwa , Yu-Der Chih , Yi-Chun Shih , Chien-Yin Liu
Abstract: Disclosed is a methods and apparatus which can improve defect tolerability of a hardware-based neural network. In one embodiment, a method for performing a calculation of values on first neurons of a first layer in a neural network, includes: receiving a first pattern of a memory cell array; determining a second pattern of the memory cell array according to a third pattern; determining at least one pair of columns of the memory cell array according to the first pattern and the second pattern; switching input data of two columns of each of the at least one pair of columns of the memory cell array; and switching output data of the two columns in each of the at least one pair of columns of the memory cell array so as to determine the values on the first neurons of the first layer.
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公开(公告)号：US10937467B2
公开(公告)日：2021-03-02
申请号：US16660588
申请日：2019-10-22
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Po-Hao Lee , Yi-Chun Shih
Abstract: A device includes a circuit cell, a first switching unit, and a second switching unit. The first switching unit is configured to output an auxiliary signal. The second switching unit is coupled between the first switching unit and the circuit cell, and configured to transmit a write voltage and an auxiliary signal to the circuit cell.
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公开(公告)号：US10288494B2
公开(公告)日：2019-05-14
申请号：US15591976
申请日：2017-05-10
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shih-Lien Linus Lu , Chia-Fu Lee , Yi-Chun Shih , Chung-Cheng Chou , Yu-Der Chih
Abstract: A thermometer circuit configured to estimate a monitored temperature is disclosed. The circuit includes an adjustable resistor presenting a first resistance value that is temperature-independent and a second resistance value that is temperature-dependent, wherein a first current signal is conducted across the resistor when it presents the first resistance value and a second current signal is conducted across the resistor when it presents the second resistance value; a plurality of gated conductors coupled to the resistor; and a control circuit, coupled to the resistor and the plurality of gated conductors, and configured to selectively deactivate at least one of the plurality of gated conductors to compare the first and second current signals to estimate the monitored temperature.
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Patent Agency Ranking
公开(公告)号：US09754639B2
公开(公告)日：2017-09-05
申请号：US14929076
申请日：2015-10-30
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Chia-Fu Lee , Yu-Der Chih , Hon-Jarn Lin , Yi-Chun Shih
CPC classification number: G11C11/1673 , G11C7/062 , G11C7/22 , G11C11/161 , G11C13/004 , G11C2013/0045 , G11C2013/0054 , G11C2013/0057 , G11C2207/063
Abstract: A device is disclosed that includes memory cells, a reference circuit, and a sensing unit. Each of the memory cells is configured to store bit data. The reference circuit includes reference switches and reference storage units. The reference switches are disposed. A first reference storage unit of the reference storage units is configured to generate a first signal having a first logic state when a first reference switch the reference switches is turned on. A second reference storage unit of the reference storage units is configured to generate a second signal having a second logic state when a second reference switch of the reference switches is turned on. The sensing unit is configured to determine a logic state of the bit data of one of the memory cells according to the first signal and the second signal.
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公开(公告)号：US09620209B2
公开(公告)日：2017-04-11
申请号：US15238167
申请日：2016-08-16
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Yi-Chun Shih , Chung-Cheng Chou , Po-Hao Lee
CPC classification number: G11C13/0069 , G11C13/0026 , G11C13/0038 , G11C13/0064 , G11C2013/0054 , G11C2013/0066 , G11C2213/79
Abstract: Circuits and methods for limiting cell current or throttling write operation, or both, in resistive random access memory (RRAM or ReRAM) cells are provided. An RRAM cell can include a select transistor and a programmable resistor that can change between a relatively high resistance and a relatively low resistance. The present circuits and methods can reduce or inhibit excess current from being applied to the programmable resistor, which potentially can regulate the resistance of the programmable resistor so as to reduce or inhibit decreases in the resistance of that resistor below the relatively low resistance. Such regulation potentially can improve reliability of the RRAM cell. Additionally, or alternatively, the present circuits and methods can throttle a write operation in an RRAM cell, e.g., can disable current flow through the RRAM cell based on the programmable resistor reaching a pre-defined target resistance, such as the relatively low resistance.
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公开(公告)号：US11848040B2
公开(公告)日：2023-12-19
申请号：US17559998
申请日：2021-12-22
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Chia-Fu Lee , Yu-Der Chih , Hon-Jarn Lin , Yi-Chun Shih
CPC classification number: G11C11/1673 , G11C7/062 , G11C7/22 , G11C11/161 , G11C13/004 , G11C2013/0045 , G11C2013/0054 , G11C2013/0057 , G11C2207/063
Abstract: A device includes first and second reference storage units, and first and second reference switches. The first reference switch outputs a first current at a first terminal thereof to the first reference storage unit. The first reference storage unit receives the first current at a first terminal thereof and generates a first signal, according to the first current, at a second terminal thereof to an average current circuit. The second reference switch outputs a second current at a first terminal thereof to the second reference storage unit. The second reference storage unit receives the second current at a first terminal thereof, and generates a second signal, according to the second current, at a second terminal thereof to the average current circuit. The first and second reference switches are coupled to a plurality of first memory cells by a first word line.
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公开(公告)号：US11797034B2
公开(公告)日：2023-10-24
申请号：US17339818
申请日：2021-06-04
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yen-An Chang , Chia-Fu Lee , Yu-Der Chih , Yi-Chun Shih
IPC: G05F1/56
CPC classification number: G05F1/56
Abstract: A voltage regulation circuit includes a voltage regulator that is configured to provide a stable output voltage based on an input voltage; and a control circuit, coupled to the voltage regulator, and configured to provide an injection current to maintain the stable output voltage in response to an enable signal provided at an input of the control circuit transitioning to a predetermined state and cease providing the injection current when the control circuit detects that a voltage level of the output voltage is higher than a pre-defined voltage level.
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公开(公告)号：US20220383085A1
公开(公告)日：2022-12-01
申请号：US17883594
申请日：2022-08-08
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Win-San Khwa , Yu-Der Chih , Yi-Chun Shih , Chien-Yin Liu
Abstract: Disclosed is a methods and apparatus which can improve defect tolerability of a hardware-based neural network. In one embodiment, a method for performing a calculation of values on first neurons of a first layer in a neural network, includes: receiving a first pattern of a memory cell array; determining a second pattern of the memory cell array according to a third pattern; determining at least one pair of columns of the memory cell array according to the first pattern and the second pattern; switching input data of two columns of each of the at least one pair of columns of the memory cell array; and switching output data of the two columns in each of the at least one pair of columns of the memory cell array so as to determine the values on the first neurons of the first layer.
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