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公开(公告)号：US11556414B2
公开(公告)日：2023-01-17
申请号：US17222919
申请日：2021-04-05
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chien-Yin Liu , Yu-Der Chih , Hsueh-Chih Yang , Jonathan Tehan Chen , Kuan-Chun Chen
Abstract: A method includes: retrieving a first word comprising a plurality of data bits and a plurality of parity bits that correspond to the first word, wherein the plurality of data bits form N−1 groups and the plurality of parity bits form a first group different from the N−1 groups, and N is a positive integer greater than 2; receiving a request to update respective data bits of a first one of the N−1 groups; and providing a second word comprising updated data bits that form a second one of the N−1 groups and a plurality of updated parity bits that correspond to the second word, wherein the plurality of updated parity bits form a second group that has a same group index as the first one of the N−1 groups.
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公开(公告)号：US10599517B2
公开(公告)日：2020-03-24
申请号：US15965883
申请日：2018-04-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chien-Yin Liu , Yu-Der Chih , Hsueh-Chih Yang , Jonathan Tehan Chen , Kuan-Chun Chen
Abstract: A method includes: retrieving a first word comprising a plurality of data bits and a plurality of parity bits that correspond to the first word, wherein the plurality of data bits form N−1 groups and the plurality of parity bits form a first group different from the N−1 groups, and N is a positive integer greater than 2; receiving a request to update respective data bits of a first one of the N−1 groups; and providing a second word comprising updated data bits that form a second one of the N−1 groups and a plurality of updated parity bits that correspond to the second word, wherein the plurality of updated parity bits form a second group that has a same group index as the first one of the N−1 groups.
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公开(公告)号：US12205017B2
公开(公告)日：2025-01-21
申请号：US18231769
申请日：2023-08-08
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Win-San Khwa , Yu-Der Chih , Yi-Chun Shih , Chien-Yin Liu
Abstract: Disclosed is a methods and apparatus which can improve defect tolerability of a hardware-based neural network. In one embodiment, a method for performing a calculation of values on first neurons of a first layer in a neural network, includes: receiving a first pattern of a memory cell array; determining a second pattern of the memory cell array according to a third pattern; determining at least one pair of columns of the memory cell array according to the first pattern and the second pattern; switching input data of two columns of each of the at least one pair of columns of the memory cell array; and switching output data of the two columns in each of the at least one pair of columns of the memory cell array so as to determine the values on the first neurons of the first layer.
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公开(公告)号：US11461623B2
公开(公告)日：2022-10-04
申请号：US16542049
申请日：2019-08-15
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Win-San Khwa , Yu-Der Chih , Yi-Chun Shih , Chien-Yin Liu
Abstract: Disclosed is a methods and apparatus which can improve defect tolerability of a hardware-based neural network. In one embodiment, a method for performing a calculation of values on first neurons of a first layer in a neural network, includes: receiving a first pattern of a memory cell array; determining a second pattern of the memory cell array according to a third pattern; determining at least one pair of columns of the memory cell array according to the first pattern and the second pattern; switching input data of two columns of each of the at least one pair of columns of the memory cell array; and switching output data of the two columns in each of the at least one pair of columns of the memory cell array so as to determine the values on the first neurons of the first layer.
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公开(公告)号：US09812182B2
公开(公告)日：2017-11-07
申请号：US15250212
申请日：2016-08-29
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Yue-Der Chih , Cheng-Hsiung Kuo , Gu-Huan Li , Chien-Yin Liu
CPC classification number: G11C7/20 , G11C5/02 , G11C11/1659 , G11C11/1677 , G11C11/406 , G11C13/0033 , G11C13/0064 , G11C13/0069 , G11C2013/0076
Abstract: A method and a system for memory cell programming and erasing with refreshing operation are disclosed. The system includes a selecting module, a processing module and a refresh module. In the method, at first, a target memory cell from a plurality of memory cells in a memory device is selected. Thereafter, the target memory cell belonging to a line of the matrix is programmed or erased by applying a selecting voltage on the target memory cell and a location-related memory cell belonging to the line of the matrix. Then, a refreshing operation to refresh the location-related cell is performed.
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Patent Agency Ranking
公开(公告)号：US09208847B2
公开(公告)日：2015-12-08
申请号：US14067907
申请日：2013-10-30
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Yue-Der Chih , Cheng-Hsiung Kuo , Gu-Huan Li , Chien-Yin Liu
CPC classification number: G11C7/20 , G11C5/02 , G11C11/1659 , G11C11/1677 , G11C11/406 , G11C13/0033 , G11C13/0064 , G11C13/0069 , G11C2013/0076
Abstract: A method and a system for memory cell programming and erasing with refreshing operation are disclosed. The system includes a selecting module, a processing module and a refresh module. In the method, at first, a target memory cell from a plurality of memory cells in a memory device is selected. Thereafter, the target memory cell belonging to a line of the matrix is programmed or erased by applying a selecting voltage on the target memory cell and a location-related memory cell belonging to the line of the matrix. Then, a refreshing operation to refresh the location-related cell is performed.
Abstract translation: 公开了一种用于具有刷新操作的存储器单元编程和擦除的方法和系统。 该系统包括选择模块，处理模块和刷新模块。 在该方法中，首先，选择来自存储装置中的多个存储单元的目标存储单元。 此后，通过对目标存储单元施加选择电压和属于矩阵行的位置相关的存储单元来对属于矩阵行的目标存储单元进行编程或擦除。 然后，执行刷新位置相关单元的刷新操作。
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公开(公告)号：US11797831B2
公开(公告)日：2023-10-24
申请号：US17883594
申请日：2022-08-08
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Win-San Khwa , Yu-Der Chih , Yi-Chun Shih , Chien-Yin Liu
CPC classification number: G06N3/063 , G06N3/08 , G11C11/54 , G11C29/04 , G11C7/1006
Abstract: Disclosed is a methods and apparatus which can improve defect tolerability of a hardware-based neural network. In one embodiment, a method for performing a calculation of values on first neurons of a first layer in a neural network, includes: receiving a first pattern of a memory cell array; determining a second pattern of the memory cell array according to a third pattern; determining at least one pair of columns of the memory cell array according to the first pattern and the second pattern; switching input data of two columns of each of the at least one pair of columns of the memory cell array; and switching output data of the two columns in each of the at least one pair of columns of the memory cell array so as to determine the values on the first neurons of the first layer.
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公开(公告)号：US11043249B2
公开(公告)日：2021-06-22
申请号：US16676290
申请日：2019-11-06
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Yue-Der Chih , Cheng-Hsiung Kuo , Gu-Huan Li , Chien-Yin Liu
IPC: G11C7/20 , G11C11/406 , G11C11/16 , G11C13/00 , G11C5/02
Abstract: A memory device for memory cell programming and erasing with refreshing operation is disclosed. The memory device includes a location-related memory cell and a refresh module. The location-related memory cell is coupled to a bit line. The refresh module is configured to refresh the location-related memory cell by reading data stored in the location-related memory cell and then writing the data back to the location-related memory cell in a condition that a target memory cell that is coupled to the bit line is programmed or erased. A method for memory cell programming and erasing with refreshing operation is also disclosed herein.
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公开(公告)号：US10970167B2
公开(公告)日：2021-04-06
申请号：US16743445
申请日：2020-01-15
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chien-Yin Liu , Yu-Der Chih , Hsueh-Chih Yang , Jonathan Tehan Chen , Kuan-Chun Chen
Abstract: A method includes: retrieving a first word comprising a plurality of data bits and a plurality of parity bits that correspond to the first word, wherein the plurality of data bits form N−1 groups and the plurality of parity bits form a first group different from the N−1 groups, and N is a positive integer greater than 2; receiving a request to update respective data bits of a first one of the N−1 groups; and providing a second word comprising updated data bits that form a second one of the N−1 groups and a plurality of updated parity bits that correspond to the second word, wherein the plurality of updated parity bits form a second group that has a same group index as the first one of the N−1 groups.
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公开(公告)号：US11935620B2
公开(公告)日：2024-03-19
申请号：US17353592
申请日：2021-06-21
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Yue-Der Chih , Cheng-Hsiung Kuo , Gu-Huan Li , Chien-Yin Liu
CPC classification number: G11C7/20 , G11C5/02 , G11C11/1659 , G11C11/1677 , G11C11/406 , G11C13/0033 , G11C13/0064 , G11C13/0069 , G11C2013/0076
Abstract: A memory device for memory cell programming and erasing with refreshing operation is disclosed. The memory device includes multiple location-related memory cells and a refresh module. The location-related memory cells are coupled to a bit line on which a selecting voltage is applied. The refresh module rewrites a stored data of a first cell of the location-related memory cells to the first cell of the location-related memory cells in response to an operation count being smaller than a number N. N is related to the number of the location-related memory cells.
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