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公开(公告)号：US12164317B2
公开(公告)日：2024-12-10
申请号：US18232772
申请日：2023-08-10
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yen-An Chang , Chia-Fu Lee , Yu-Der Chih , Yi-Chun Shih
IPC: G05F1/56
Abstract: A voltage regulation circuit includes a voltage regulator that is configured to provide a stable output voltage based on an input voltage; and a control circuit, coupled to the voltage regulator, and configured to provide an injection current to maintain the stable output voltage in response to an enable signal provided at an input of the control circuit transitioning to a predetermined state and cease providing the injection current when the control circuit detects that a voltage level of the output voltage is higher than a pre-defined voltage level.
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公开(公告)号：US11373690B2
公开(公告)日：2022-06-28
申请号：US17156383
申请日：2021-01-22
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Ku-Feng Lin , Yu-Der Chih , Yi-Chun Shih , Chia-Fu Lee
Abstract: Circuits and methods for compensating mismatches in sense amplifiers are disclosed. In one example, a circuit is disclosed. The circuit includes: a first branch, a second branch, a first plurality of trimming transistors and a second plurality of trimming transistors. The first branch comprises a first transistor, a second transistor, and a first node coupled between the first transistor and the second transistor. The second branch comprises a third transistor, a fourth transistor, and a second node coupled between the third transistor and the fourth transistor. The first node is coupled to respective gates of the third transistor and the fourth transistor. The second node is coupled to respective gates of the first transistor and the second transistor. The first plurality of trimming transistors is coupled to the second transistor in parallel. The second plurality of trimming transistors is coupled to the fourth transistor in parallel.
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公开(公告)号：US09904593B2
公开(公告)日：2018-02-27
申请号：US14941126
申请日：2015-11-13
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Chia-Fu Lee , Yu-Der Chih
CPC classification number: G06F11/1068 , G06F11/1048 , G06F11/1076 , G11C7/06 , G11C7/08 , G11C7/14 , G11C11/1673 , G11C13/004 , G11C29/021 , G11C29/022 , G11C29/026 , G11C29/44 , G11C29/52 , G11C2013/0054 , G11C2029/0409
Abstract: A device includes a reference circuit, a readout circuit, and an error correction coding circuit. The reference circuit is configured to generate a reference signal. The readout circuit is configured to generate data values of second data according to the reference signal and first data. The error correction coding circuit is configured to reset the reference circuit when errors occur in all of the data values of the second data.
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公开(公告)号：US20230393598A1
公开(公告)日：2023-12-07
申请号：US18232772
申请日：2023-08-10
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yen-An CHANG , Chia-Fu Lee , Yu-Der Chih , Yi-Chun Shih
IPC: G05F1/56
CPC classification number: G05F1/56
Abstract: A voltage regulation circuit includes a voltage regulator that is configured to provide a stable output voltage based on an input voltage; and a control circuit, coupled to the voltage regulator, and configured to provide an injection current to maintain the stable output voltage in response to an enable signal provided at an input of the control circuit transitioning to a predetermined state and cease providing the injection current when the control circuit detects that a voltage level of the output voltage is higher than a pre-defined voltage level.
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公开(公告)号：US10288494B2
公开(公告)日：2019-05-14
申请号：US15591976
申请日：2017-05-10
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Shih-Lien Linus Lu , Chia-Fu Lee , Yi-Chun Shih , Chung-Cheng Chou , Yu-Der Chih
Abstract: A thermometer circuit configured to estimate a monitored temperature is disclosed. The circuit includes an adjustable resistor presenting a first resistance value that is temperature-independent and a second resistance value that is temperature-dependent, wherein a first current signal is conducted across the resistor when it presents the first resistance value and a second current signal is conducted across the resistor when it presents the second resistance value; a plurality of gated conductors coupled to the resistor; and a control circuit, coupled to the resistor and the plurality of gated conductors, and configured to selectively deactivate at least one of the plurality of gated conductors to compare the first and second current signals to estimate the monitored temperature.
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Patent Agency Ranking
公开(公告)号：US09899079B2
公开(公告)日：2018-02-20
申请号：US15018726
申请日：2016-02-08
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Chih-Yang Chang , Chia-Fu Lee , Wen-Ting Chu , Yue-Der Chih
CPC classification number: G11C13/0026 , G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2013/009 , G11C2213/79 , H01L27/2436 , H01L27/2463 , H01L45/16
Abstract: A device is disclosed that includes memory cells, bit lines and a source line. The bit lines and the source line are electrically connected to the memory cells. In the I/O memory block, the source line and the bit lines are configured to provide logical data to the memory cells.
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公开(公告)号：US09754639B2
公开(公告)日：2017-09-05
申请号：US14929076
申请日：2015-10-30
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Chia-Fu Lee , Yu-Der Chih , Hon-Jarn Lin , Yi-Chun Shih
CPC classification number: G11C11/1673 , G11C7/062 , G11C7/22 , G11C11/161 , G11C13/004 , G11C2013/0045 , G11C2013/0054 , G11C2013/0057 , G11C2207/063
Abstract: A device is disclosed that includes memory cells, a reference circuit, and a sensing unit. Each of the memory cells is configured to store bit data. The reference circuit includes reference switches and reference storage units. The reference switches are disposed. A first reference storage unit of the reference storage units is configured to generate a first signal having a first logic state when a first reference switch the reference switches is turned on. A second reference storage unit of the reference storage units is configured to generate a second signal having a second logic state when a second reference switch of the reference switches is turned on. The sensing unit is configured to determine a logic state of the bit data of one of the memory cells according to the first signal and the second signal.
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公开(公告)号：US20170140819A1
公开(公告)日：2017-05-18
申请号：US15332371
申请日：2016-10-24
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chia-Fu Lee , Yu-Der Chih , Hon-Jarn Lin
IPC: G11C13/00
CPC classification number: G11C13/0069 , G11C13/0023 , G11C13/0026 , G11C13/0038 , G11C13/004 , G11C2013/0083 , G11C2013/0088 , G11C2213/79 , G11C2213/82
Abstract: The present disclosure relates to a RRAM circuit comprising a current limiting element configured to improve forming time of RRAM cells, and an associated method. In some embodiments, the RRAM circuit has an RRAM array with a plurality of RRAM devices. A bit-line decoder is configured to concurrently apply a forming signal to a plurality of bit-lines coupled to two or more of the plurality of RRAM devices in a row of the RRAM array. A current limiting element is configured to concurrently limit a current on the plurality of bit-lines to below a forming value during a forming operation that forms conductive filaments within the RRAM devices. By limiting the current on the bit-lines during the forming operation, a forming signal can concurrently be applied to multiple RRAM devices while maintaining a relatively low overall power consumption, thereby allowing for the forming operation to be performed quickly.
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公开(公告)号：US11848040B2
公开(公告)日：2023-12-19
申请号：US17559998
申请日：2021-12-22
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Chia-Fu Lee , Yu-Der Chih , Hon-Jarn Lin , Yi-Chun Shih
CPC classification number: G11C11/1673 , G11C7/062 , G11C7/22 , G11C11/161 , G11C13/004 , G11C2013/0045 , G11C2013/0054 , G11C2013/0057 , G11C2207/063
Abstract: A device includes first and second reference storage units, and first and second reference switches. The first reference switch outputs a first current at a first terminal thereof to the first reference storage unit. The first reference storage unit receives the first current at a first terminal thereof and generates a first signal, according to the first current, at a second terminal thereof to an average current circuit. The second reference switch outputs a second current at a first terminal thereof to the second reference storage unit. The second reference storage unit receives the second current at a first terminal thereof, and generates a second signal, according to the second current, at a second terminal thereof to the average current circuit. The first and second reference switches are coupled to a plurality of first memory cells by a first word line.
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公开(公告)号：US11797034B2
公开(公告)日：2023-10-24
申请号：US17339818
申请日：2021-06-04
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yen-An Chang , Chia-Fu Lee , Yu-Der Chih , Yi-Chun Shih
IPC: G05F1/56
CPC classification number: G05F1/56
Abstract: A voltage regulation circuit includes a voltage regulator that is configured to provide a stable output voltage based on an input voltage; and a control circuit, coupled to the voltage regulator, and configured to provide an injection current to maintain the stable output voltage in response to an enable signal provided at an input of the control circuit transitioning to a predetermined state and cease providing the injection current when the control circuit detects that a voltage level of the output voltage is higher than a pre-defined voltage level.
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