公开(公告)号：US20210174856A1

公开(公告)日：2021-06-10

申请号：US17177627

申请日：2021-02-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Yu Chen ,  Kuo-Chi Tu ,  Wen-Ting Chu ,  Yong-Shiuan Tsair

IPC: G11C11/22 ,  H01L27/11592 ,  H01L29/51 ,  H01L27/1159

Abstract: The present disclosure relates to a method of forming a memory structure. The method includes depositing a ferroelectric random access memory (FeRAM) stack over a substrate. The FeRAM stack has a ferroelectric layer and one or more conductive layers over the ferroelectric layer. The FeRAM stack is patterned to define an FeRAM device stack. A sidewall spacer is formed along a first side of the FeRAM device stack, and a select gate is formed along a side of the sidewall spacer that faces away from the FeRAM device stack. A source region is formed within the substrate and along a second side of the FeRAM device stack, and a drain region is formed within the substrate. The drain region is separated from the FeRAM device stack by the select gate.

公开(公告)号：US20210036057A1

公开(公告)日：2021-02-04

申请号：US16575663

申请日：2019-09-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Te-Hsien Hsieh ,  Tzu-Yu Chen ,  Kuo-Chi Tu ,  Yuan-Tai Tseng

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

Abstract: An RRAM cell stack is formed over an opening in a dielectric layer. The dielectric layer is sufficiently thick and the opening is sufficiently deep that an RRAM cell can be formed by a planarization process. The resulting RRAM cells may have a U-shaped profile. The RRAM cell area includes contributions from a bottom portion in which the RRAM cell layers are stacked parallel to the substrate and a side portion in which RRAM cell layers are stacked roughly perpendicular to the substrate. The combined side and bottom portions of the curved RRAM cell provide an increased area in comparison to a planar cell stack. The increased area lowers forming and set voltages for the RRAM cell.

公开(公告)号：US10763270B2

公开(公告)日：2020-09-01

申请号：US15964702

申请日：2018-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Yu Chen ,  Kuo-Chi Tu ,  Wen-Ting Chu ,  Yong-Shiuan Tsair

IPC: H01L27/11507 ,  H01L27/11509 ,  H01L21/311 ,  H01L29/66 ,  H01L21/762 ,  H01L29/78 ,  H01L29/06 ,  H01L21/266 ,  H01L21/321 ,  H01L29/51 ,  H01L21/3105 ,  H01L29/08 ,  H01L21/265

Abstract: A method for forming an integrated circuit (IC) and an IC are disclosed. The method for forming the IC includes: forming an isolation structure separating a memory semiconductor region from a logic semiconductor region; forming a memory cell structure on the memory semiconductor region; forming a memory capping layer covering the memory cell structure and the logic semiconductor region; performing a first etch into the memory capping layer to remove the memory capping layer from the logic semiconductor region, and to define a slanted, logic-facing sidewall on the isolation structure; forming a logic device structure on the logic semiconductor region; and performing a second etch into the memory capping layer to remove the memory capping layer from the memory semiconductor, while leaving a dummy segment of the memory capping layer that defines the logic-facing sidewall.

公开(公告)号：US20200006360A1

公开(公告)日：2020-01-02

申请号：US16558750

申请日：2019-09-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Yu Chen ,  Kuo-Chi Tu ,  Wen-Ting Chu ,  Yong-Shiuan Tsair

IPC: H01L27/11507 ,  H01L21/311 ,  H01L27/11509 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762

Abstract: A method for forming an integrated circuit (IC) and an IC are disclosed. The method for forming the IC includes: forming an isolation structure separating a memory semiconductor region from a logic semiconductor region; forming a memory cell structure on the memory semiconductor region; forming a memory capping layer covering the memory cell structure and the logic semiconductor region; performing a first etch into the memory capping layer to remove the memory capping layer from the logic semiconductor region, and to define a slanted, logic-facing sidewall on the isolation structure; forming a logic device structure on the logic semiconductor region; and performing a second etch into the memory capping layer to remove the memory capping layer from the memory semiconductor, while leaving a dummy segment of the memory capping layer that defines the logic-facing sidewall.

公开(公告)号：US20220231034A1

公开(公告)日：2022-07-21

申请号：US17712495

申请日：2022-04-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Yu Chen ,  Kuo-Chi Tu ,  Fu-Chen Chang ,  Chih-Hsiang Chang ,  Sheng-Hung Shih

IPC: H01L27/11507 ,  H01L27/11504 ,  G11C11/22 ,  H01L49/02

Abstract: In an embodiment, a structure includes one or more first transistors in a first region of a device, the one or more first transistors supporting a memory access function of the device. The structure includes one or more ferroelectric random access memory (FeRAM) capacitors in a first inter-metal dielectric (IMD) layer over the one or more first transistors in the first region. The structure also includes one or more metal-ferroelectric insulator-metal (MFM) decoupling capacitors in the first IMD layer in a second region of the device. The MFM capacitors may include two or more capacitors coupled in series to act as a voltage divider.

公开(公告)号：US11257844B2

公开(公告)日：2022-02-22

申请号：US16569487

申请日：2019-09-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tzu-Yu Chen ,  Sheng-Hung Shih ,  Kuo-Chi Tu ,  Wen-Ting Chu

IPC: H01L27/1159 ,  H01L23/522

Abstract: A semiconductor device includes a lower intermetal dielectric (IMD) layer, a middle conductive line, and a ferroelectric random access memory (FRAM) structure. The middle conductive line is embedded in the lower IMD layer. The FRAM structure is over the lower IMD layer and the middle conductive line. The FRAM structure includes a bottom electrode, a ferroelectric layer, and a top electrode. The bottom electrode is over the middle conductive line and in contact with the lower IMD layer. The ferroelectric layer is over the bottom electrode. The top electrode is over the ferroelectric layer.

公开(公告)号：US20210343731A1

公开(公告)日：2021-11-04

申请号：US17376531

申请日：2021-07-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Yu Chen ,  Kuo-Chi Tu ,  Sheng-Hung Shih ,  Fu-Chen Chang

IPC: H01L27/11507 ,  H01L49/02

Abstract: Some embodiments relate to a ferroelectric random access memory (FeRAM) device. The FeRAM device includes a bottom electrode structure and a top electrode overlying the ferroelectric structure. The top electrode has a first width as measured between outermost sidewalls of the top electrode. A ferroelectric structure separates the bottom electrode structure from the top electrode. The ferroelectric structure has a second width as measured between outermost sidewalls of the ferroelectric structure. The second width is greater than the first width such that the ferroelectric structure includes a ledge that reflects a difference between the first width and the second width. A dielectric sidewall spacer structure is disposed on the ledge and covers the outermost sidewalls of the top electrode.

公开(公告)号：US10930333B2

公开(公告)日：2021-02-23

申请号：US16267668

申请日：2019-02-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Yu Chen ,  Kuo-Chi Tu ,  Wen-Ting Chu ,  Yong-Shiuan Tsair

IPC: H01L21/00 ,  G11C11/22 ,  H01L27/11592 ,  H01L27/1159 ,  H01L29/51

Abstract: In some embodiments, the present disclosure relates to a memory structure. The memory structure has a source region and a drain region disposed within a substrate. A select gate disposed over the substrate between the source region and the drain region. A ferroelectric random access memory (FeRAM) device is disposed over the substrate between the select gate and the source region. The FeRAM device includes a ferroelectric material arranged between the substrate and a conductive electrode.

公开(公告)号：US20210035992A1

公开(公告)日：2021-02-04

申请号：US16663952

申请日：2019-10-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Yu Chen ,  Kuo-Chi Tu ,  Sheng-Hung Shih ,  Wen-Ting Chu ,  Chih-Hsiang Chang ,  Fu-Chen Chang

IPC: H01L27/11502

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a plurality of lower interconnect layers disposed within a lower dielectric structure over a substrate. A lower insulating structure is over the lower dielectric structure and has sidewalls extending through the lower insulating structure. A bottom electrode is arranged along the sidewalls and an upper surface of the lower insulating structure. The upper surface of the lower insulating structure extends past outermost sidewalls of the bottom electrode. A data storage structure is disposed on the bottom electrode and is configured to store a data state. A top electrode is disposed on the data storage structure. The bottom electrode has interior sidewalls coupled to a horizontally extending surface to define a recess within an upper surface of the bottom electrode. The horizontally extending surface is below the upper surface of the lower insulating structure.

公开(公告)号：US20170194344A1

公开(公告)日：2017-07-06

申请号：US14984095

申请日：2015-12-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei Cheng Wu ,  Tzu-Yu Chen

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/423 ,  H01L29/792 ,  H01L29/66

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L27/1157 ,  H01L29/42344 ,  H01L29/6656 ,  H01L29/66833 ,  H01L29/792

Abstract: The present disclosure relates to an integrated circuit (IC) that includes a high-k metal gate (HKMG) non-volatile memory (NVM) device and that provides small scale and high performance, and a method of formation. In some embodiments, the integrated circuit includes a memory region having a select transistor and a control transistor laterally spaced apart over a substrate. A select gate electrode and a control gate electrode are disposed over a high-k gate dielectric layer and a memory gate oxide. A logic region is disposed adjacent to the memory region and has a logic device including a metal gate electrode disposed over the high-k gate dielectric layer and a logic gate oxide. The select gate electrode and the control gate electrode can be polysilicon electrodes.