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公开(公告)号：US20210111333A1
公开(公告)日：2021-04-15
申请号：US16601723
申请日：2019-10-15
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yao-Wen Chang , Chung-Chiang Min , Harry-Hak-Lay Chuang , Hung Cho Wang , Tsung-Hsueh Yang , Yuan-Tai Tseng , Sheng-Huang Huang , Chia-Hua Lin
Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a magnetoresistive random access memory (MRAM) cell over a substrate. A dielectric structure overlies the substrate. The MRAM cell is disposed within the dielectric structure. The MRAM cell includes a magnetic tunnel junction (MTJ) sandwiched between a bottom electrode and a top electrode. A conductive wire overlies the top electrode. A sidewall spacer structure continuously extends along a sidewall of the MTJ and the top electrode. The sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and a protective sidewall spacer layer sandwiched between the first and second sidewall spacer layers. The first and second sidewall spacer layers comprise a first material and the protective sidewall spacer layer comprises a second material different than the first material.
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公开(公告)号：US20210036057A1
公开(公告)日：2021-02-04
申请号：US16575663
申请日：2019-09-19
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Te-Hsien Hsieh , Tzu-Yu Chen , Kuo-Chi Tu , Yuan-Tai Tseng
Abstract: An RRAM cell stack is formed over an opening in a dielectric layer. The dielectric layer is sufficiently thick and the opening is sufficiently deep that an RRAM cell can be formed by a planarization process. The resulting RRAM cells may have a U-shaped profile. The RRAM cell area includes contributions from a bottom portion in which the RRAM cell layers are stacked parallel to the substrate and a side portion in which RRAM cell layers are stacked roughly perpendicular to the substrate. The combined side and bottom portions of the curved RRAM cell provide an increased area in comparison to a planar cell stack. The increased area lowers forming and set voltages for the RRAM cell.
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公开(公告)号：US20200020856A1
公开(公告)日：2020-01-16
申请号：US16578304
申请日：2019-09-21
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Ming Chyi Liu , Yuan-Tai Tseng , Chern-Yow Hsu , Shih-Chang Liu , Chia-Shiung Tsai
Abstract: The present disclosure relates to a resistive random access memory (RRAM) device architecture, that includes a thin single layer of a conductive etch-stop layer between a lower metal interconnect and a bottom electrode of an RRAM cell. The conductive etch-stop layer provides simplicity in structure and the etch-selectivity of this layer provides protection to the underlying layers. The conductive etch stop layer can be etched using a dry or wet etch to land on the lower metal interconnect. In instances where the lower metal interconnect is copper, etching the conductive etch stop layer to expose the copper does not produce as much non-volatile copper etching by-products as in traditional methods. Compared to traditional methods, some embodiments of the disclosed techniques reduce the number of mask step and also reduce chemical mechanical polishing during the formation of the bottom electrode.
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公开(公告)号：US20200013953A1
公开(公告)日：2020-01-09
申请号：US16575725
申请日：2019-09-19
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Ming Chyi Liu , Yuan-Tai Tseng , Shih-Chang Liu , Chia-Shiung Tsai
Abstract: In some methods, a contact is formed over a substrate, and a bottom electrode layer is formed over the contact. A first dielectric layer is formed to cover a peripheral portion of the bottom electrode layer but not a central portion of the bottom electrode layer. A second dielectric layer is formed over the first dielectric layer. The second dielectric layer includes a central dielectric region that contacts the central portion of the bottom electrode layer, and a peripheral dielectric region over the peripheral portion of the bottom electrode. A step dielectric region connects the central and peripheral dielectric regions. A top electrode layer is formed over the second dielectric layer. The top electrode layer includes a central top electrode region, a peripheral top electrode region, and a step top electrode region directly above the central dielectric region, the peripheral dielectric region, and the step dielectric region, respectively.
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公开(公告)号：US10510763B2
公开(公告)日：2019-12-17
申请号：US15607337
申请日：2017-05-26
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Chang-Ming Wu , Wei-Cheng Wu , Yuan-Tai Tseng , Shih-Chang Liu , Chia-Shiung Tsai , Ru-Liang Lee , Harry Hak-Lay Chuang
IPC: H01L27/11521 , H01L21/28 , H01L21/3213 , H01L21/02 , H01L21/311 , H01L21/3205 , H01L29/423 , H01L29/49 , H01L29/66 , H01L29/788 , H01L21/768 , H01L23/528 , H01L23/532
Abstract: A nonvolatile memory embedded in an advanced logic circuit and a method forming the same are provided. In the nonvolatile memory, the word lines and erase gates have top surfaces lower than the top surfaces of the control gate. In addition, the word lines and the erase gates are surrounded by dielectric material before a self-aligned silicidation process is performed. Therefore, no metal silicide can be formed on the word lines and the erase gate to produce problems of short circuit and current leakage in a later chemical mechanical polishing process.
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Patent Agency Ranking
公开(公告)号：US20190122962A1
公开(公告)日：2019-04-25
申请号：US16221767
申请日：2018-12-17
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yuan-Tai Tseng , Chia-Shiung Tsai , Chung-Yen Chou , Ming-Chyi Liu
IPC: H01L23/485 , H01C17/075 , H01C7/00 , H01L21/768 , H01L23/522 , H01L49/02 , H01L21/70
Abstract: A novel integrated circuit and method thereof are provided. The integrated circuit includes a plurality of first interconnect pads, a plurality of second interconnect pads, a first inter-level dielectric layer, a thin film resistor, and at least two end-caps. The end-caps, which are connectors for the thin film resistor, are positioned at the same level with the plurality of second interconnect pads. Therefore, an electrical connection between the end-caps and the plurality of second interconnect pads can be formed by directly connection of them. An integrated circuit with a thin film resistor can be made in a cost benefit way accordingly, so as to overcome disadvantages mentioned above.
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公开(公告)号：US20190074440A1
公开(公告)日：2019-03-07
申请号：US15694297
申请日：2017-09-01
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tsung-Hsueh Yang , Shih-Chang Liu , Yuan-Tai Tseng
Abstract: A memory cell with a hard mask and a sidewall spacer of different material is provided. The memory cell comprises a bottom electrode disposed over a substrate. A switching dielectric is disposed over the bottom electrode and having a variable resistance. A top electrode is disposed over the switching dielectric. A hard mask disposed over the top electrode. A sidewall spacer extends upwardly along sidewalls of the switching dielectric, the top electrode, and the hard mask. The hard mask and the sidewall spacer have different etch selectivity. A method for manufacturing the memory cell is also provided.
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公开(公告)号：US20180309055A1
公开(公告)日：2018-10-25
申请号：US16009327
申请日：2018-06-15
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Ming Chyi Liu , Yuan-Tai Tseng , Chern-Yow Hsu , Shih-Chang Liu , Chia-Shiung Tsai
CPC classification number: H01L45/1691 , H01L27/2436 , H01L45/04 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146 , H01L45/1675
Abstract: The present disclosure relates to a resistive random access memory (RRAM) device architecture, that includes a thin single layer of a conductive etch-stop layer between a lower metal interconnect and a bottom electrode of an RRAM cell. The conductive etch-stop layer provides simplicity in structure and the etch-selectivity of this layer provides protection to the underlying layers. The conductive etch stop layer can be etched using a dry or wet etch to land on the lower metal interconnect. In instances where the lower metal interconnect is copper, etching the conductive etch stop layer to expose the copper does not produce as much non-volatile copper etching by-products as in traditional methods. Compared to traditional methods, some embodiments of the disclosed techniques reduce the number of mask step and also reduce chemical mechanical polishing during the formation of the bottom electrode.
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公开(公告)号：US10003022B2
公开(公告)日：2018-06-19
申请号：US14196361
申请日：2014-03-04
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Ming Chyi Liu , Yuan-Tai Tseng , Chern-Yow Hsu , Shih-Chang Liu , Chia-Shiung Tsai
CPC classification number: H01L45/1691 , H01L27/2436 , H01L45/04 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/145 , H01L45/146 , H01L45/1675
Abstract: The present disclosure relates to a resistive random access memory (RRAM) device architecture, that includes a thin single layer of a conductive etch-stop layer between a lower metal interconnect and a bottom electrode of an RRAM cell. The conductive etch-stop layer provides simplicity in structure and the etch-selectivity of this layer provides protection to the underlying layers. The conductive etch stop layer can be etched using a dry or wet etch to land on the lower metal interconnect. In instances where the lower metal interconnect is copper, etching the conductive etch stop layer to expose the copper does not produce as much non-volatile copper etching by-products as in traditional methods. Compared to traditional methods, some embodiments of the disclosed techniques reduce the number of mask step and also reduce chemical mechanical polishing during the formation of the bottom electrode.
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公开(公告)号：US09673205B2
公开(公告)日：2017-06-06
申请号：US14834423
申请日：2015-08-24
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Chang-Ming Wu , Wei-Cheng Wu , Yuan-Tai Tseng , Shih-Chang Liu , Chia-Shiung Tsai , Ru-Liang Lee , Harry Hak-Lay Chuang
IPC: H01L27/115 , H01L27/11521 , H01L21/02 , H01L21/28 , H01L21/311 , H01L21/3205 , H01L21/3213 , H01L29/423 , H01L29/49 , H01L29/66 , H01L29/788 , H01L21/768 , H01L23/528 , H01L23/532
CPC classification number: H01L27/11521 , H01L21/02164 , H01L21/0217 , H01L21/02532 , H01L21/02595 , H01L21/28273 , H01L21/31111 , H01L21/32055 , H01L21/32133 , H01L21/32137 , H01L21/768 , H01L23/528 , H01L23/53271 , H01L23/5329 , H01L29/42328 , H01L29/4238 , H01L29/4916 , H01L29/6656 , H01L29/66825 , H01L29/7883 , H01L2924/0002 , H01L2924/00
Abstract: A nonvolatile memory embedded in an advanced logic circuit and a method forming the same are provided. In the nonvolatile memory, the word lines and erase gates have top surfaces lower than the top surfaces of the control gate. In addition, the word lines and the erase gates are surrounded by dielectric material before a self-aligned silicidation process is performed. Therefore, no metal silicide can be formed on the word lines and the erase gate to produce problems of short circuit and current leakage in a later chemical mechanical polishing process.
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