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公开(公告)号：US20210184114A1
公开(公告)日：2021-06-17
申请号：US17171278
申请日：2021-02-09
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Fu-Chen Chang , Kuo-Chi Tu , Wen-Ting Chu , Chu-Jie Huang
Abstract: Various embodiments of the present application are directed towards a resistive random-access memory (RRAM) cell comprising a barrier layer to constrain the movement of metal cations during operation of the RRAM cell. In some embodiments, the RRAM cell further comprises a bottom electrode, a top electrode, a switching layer, and an active metal layer. The switching layer, the barrier layer, and the active metal layer are stacked between the bottom and top electrodes, and the barrier layer is between the switching and active metal layers. The barrier layer is conductive and between has a lattice constant less than that of the active metal layer.
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公开(公告)号：US20240373645A1
公开(公告)日：2024-11-07
申请号：US18777063
申请日：2024-07-18
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tzu-Yu Chen , Kuo-Chi Tu , Fu-Chen Chang , Chih-Hsiang Chang , Sheng-Hung Shih
Abstract: In an embodiment, a structure includes one or more first transistors in a first region of a device, the one or more first transistors supporting a memory access function of the device. The structure includes one or more ferroelectric random access memory (FeRAM) capacitors in a first inter-metal dielectric (IMD) layer over the one or more first transistors in the first region. The structure also includes one or more metal-ferroelectric insulator-metal (MFM) decoupling capacitors in the first IMD layer in a second region of the device. The MFM capacitors may include two or more capacitors coupled in series to act as a voltage divider.
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公开(公告)号：US11367658B2
公开(公告)日：2022-06-21
申请号：US16933676
申请日：2020-07-20
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Fu-Chen Chang , Cheng-Lin Huang , Wen-Ming Chen
IPC: H01L21/82 , H01L23/00 , H01L21/268 , H01L21/56 , H01L23/31 , H01L23/544 , H01L23/58 , H01L25/065 , H01L25/00
Abstract: An embodiment method includes providing a wafer including a first integrated circuit die, a second integrated circuit die, and a scribe line region between the first integrated circuit die and the second integrated circuit die. The method further includes forming a kerf in the scribe line region and after forming the kerf, using a mechanical sawing process to fully separate the first integrated circuit die from the second integrated circuit die. The kerf extends through a plurality of dielectric layers into a semiconductor substrate.
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公开(公告)号：US20220231034A1
公开(公告)日：2022-07-21
申请号：US17712495
申请日：2022-04-04
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tzu-Yu Chen , Kuo-Chi Tu , Fu-Chen Chang , Chih-Hsiang Chang , Sheng-Hung Shih
IPC: H01L27/11507 , H01L27/11504 , G11C11/22 , H01L49/02
Abstract: In an embodiment, a structure includes one or more first transistors in a first region of a device, the one or more first transistors supporting a memory access function of the device. The structure includes one or more ferroelectric random access memory (FeRAM) capacitors in a first inter-metal dielectric (IMD) layer over the one or more first transistors in the first region. The structure also includes one or more metal-ferroelectric insulator-metal (MFM) decoupling capacitors in the first IMD layer in a second region of the device. The MFM capacitors may include two or more capacitors coupled in series to act as a voltage divider.
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公开(公告)号：US20210343731A1
公开(公告)日：2021-11-04
申请号：US17376531
申请日：2021-07-15
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tzu-Yu Chen , Kuo-Chi Tu , Sheng-Hung Shih , Fu-Chen Chang
IPC: H01L27/11507 , H01L49/02
Abstract: Some embodiments relate to a ferroelectric random access memory (FeRAM) device. The FeRAM device includes a bottom electrode structure and a top electrode overlying the ferroelectric structure. The top electrode has a first width as measured between outermost sidewalls of the top electrode. A ferroelectric structure separates the bottom electrode structure from the top electrode. The ferroelectric structure has a second width as measured between outermost sidewalls of the ferroelectric structure. The second width is greater than the first width such that the ferroelectric structure includes a ledge that reflects a difference between the first width and the second width. A dielectric sidewall spacer structure is disposed on the ledge and covers the outermost sidewalls of the top electrode.
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Patent Agency Ranking
公开(公告)号：US11004728B2
公开(公告)日：2021-05-11
申请号：US16741078
申请日：2020-01-13
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yu-Sheng Tang , Fu-Chen Chang , Cheng-Lin Huang , Wen-Ming Chen , Chun-Yen Lo , Kuo-Chio Liu
IPC: H01L23/544 , H01L23/28 , H01L21/78 , H01L23/495 , H01L23/522 , H01L21/304 , H01L21/768 , H01L21/683 , H01L21/67 , H01L23/00 , H01L23/48 , H01L23/498 , H01L25/10 , H01L23/58 , H01L25/065 , H01L25/00
Abstract: A method for sawing a semiconductor wafer is provided. The method includes sawing a semiconductor wafer to form a first opening. In addition, the semiconductor wafer includes a dicing tape and a substrate attached to the dicing tape by a die attach film (DAF), and the first opening is formed in an upper portion of the substrate. The method further includes sawing through the substrate and the DAF of the semiconductor wafer from the first opening to form a middle opening under the first opening and a second opening under the middle opening, so that the semiconductor wafer is divided into two dies. In addition, a slope of a sidewall of the middle opening is different from slopes of sidewalls of the first opening and the second opening.
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公开(公告)号：US20210035992A1
公开(公告)日：2021-02-04
申请号：US16663952
申请日：2019-10-25
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tzu-Yu Chen , Kuo-Chi Tu , Sheng-Hung Shih , Wen-Ting Chu , Chih-Hsiang Chang , Fu-Chen Chang
IPC: H01L27/11502
Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a plurality of lower interconnect layers disposed within a lower dielectric structure over a substrate. A lower insulating structure is over the lower dielectric structure and has sidewalls extending through the lower insulating structure. A bottom electrode is arranged along the sidewalls and an upper surface of the lower insulating structure. The upper surface of the lower insulating structure extends past outermost sidewalls of the bottom electrode. A data storage structure is disposed on the bottom electrode and is configured to store a data state. A top electrode is disposed on the data storage structure. The bottom electrode has interior sidewalls coupled to a horizontally extending surface to define a recess within an upper surface of the bottom electrode. The horizontally extending surface is below the upper surface of the lower insulating structure.
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公开(公告)号：US12114509B2
公开(公告)日：2024-10-08
申请号：US17712495
申请日：2022-04-04
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tzu-Yu Chen , Kuo-Chi Tu , Fu-Chen Chang , Chih-Hsiang Chang , Sheng-Hung Shih
CPC classification number: H10B53/30 , G11C11/221 , H01L28/56 , H01L28/75 , H10B53/10
Abstract: In an embodiment, a structure includes one or more first transistors in a first region of a device, the one or more first transistors supporting a memory access function of the device. The structure includes one or more ferroelectric random access memory (FeRAM) capacitors in a first inter-metal dielectric (IMD) layer over the one or more first transistors in the first region. The structure also includes one or more metal-ferroelectric insulator-metal (MFM) decoupling capacitors in the first IMD layer in a second region of the device. The MFM capacitors may include two or more capacitors coupled in series to act as a voltage divider.
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公开(公告)号：US11611038B2
公开(公告)日：2023-03-21
申请号：US17171278
申请日：2021-02-09
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Fu-Chen Chang , Kuo-Chi Tu , Wen-Ting Chu , Chu-Jie Huang
Abstract: Various embodiments of the present application are directed towards a resistive random-access memory (RRAM) cell comprising a barrier layer to constrain the movement of metal cations during operation of the RRAM cell. In some embodiments, the RRAM cell further comprises a bottom electrode, a top electrode, a switching layer, and an active metal layer. The switching layer, the barrier layer, and the active metal layer are stacked between the bottom and top electrodes, and the barrier layer is between the switching and active metal layers. The barrier layer is conductive and between has a lattice constant less than that of the active metal layer.
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公开(公告)号：US10950784B2
公开(公告)日：2021-03-16
申请号：US16434414
申请日：2019-06-07
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Fu-Chen Chang , Kuo-Chi Tu , Wen-Ting Chu , Chu-Jie Huang
Abstract: Various embodiments of the present application are directed towards a resistive random-access memory (RRAM) cell comprising a barrier layer to constrain the movement of metal cations during operation of the RRAM cell. In some embodiments, the RRAM cell further comprises a bottom electrode, a top electrode, a switching layer, and an active metal layer. The switching layer, the barrier layer, and the active metal layer are stacked between the bottom and top electrodes, and the barrier layer is between the switching and active metal layers. The barrier layer is conductive and has a lattice constant less than that of the active metal layer.
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