公开(公告)号：US20210184114A1

公开(公告)日：2021-06-17

申请号：US17171278

申请日：2021-02-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-Chen Chang ,  Kuo-Chi Tu ,  Wen-Ting Chu ,  Chu-Jie Huang

IPC: H01L45/00 ,  H01L27/24

Abstract: Various embodiments of the present application are directed towards a resistive random-access memory (RRAM) cell comprising a barrier layer to constrain the movement of metal cations during operation of the RRAM cell. In some embodiments, the RRAM cell further comprises a bottom electrode, a top electrode, a switching layer, and an active metal layer. The switching layer, the barrier layer, and the active metal layer are stacked between the bottom and top electrodes, and the barrier layer is between the switching and active metal layers. The barrier layer is conductive and between has a lattice constant less than that of the active metal layer.

公开(公告)号：US11017852B2

公开(公告)日：2021-05-25

申请号：US16700936

申请日：2019-12-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Chi Tu ,  Chu-Jie Huang ,  Sheng-Hung Shih ,  Nai-Chao Su ,  Wen-Ting Chu

IPC: G11C5/02 ,  G11C13/00 ,  H01L21/02 ,  H01L45/00 ,  H01L27/24 ,  H01L21/321

Abstract: A method of forming a memory device includes: forming a polish stop layer over a metallization layer in an inter-metal dielectric layer; performing an etching process to form an opening in the polish stop layer, in which a sidewall of the opening extends at an acute angle relative to a top surface of the polish stop layer; forming an electrode material in the opening and over the polish stop layer; planarizing the electrode material until a top surface of the polish stop layer is exposed so as to form a bottom electrode surrounded by the polish stop layer; and forming a stack of a resistance switching layer and a top electrode over the bottom electrode.

公开(公告)号：US11011224B2

公开(公告)日：2021-05-18

申请号：US16700918

申请日：2019-12-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Chi Tu ,  Chu-Jie Huang ,  Sheng-Hung Shih ,  Nai-Chao Su ,  Wen-Ting Chu

IPC: G11C11/34 ,  G11C13/00 ,  H01L21/02 ,  H01L45/00 ,  H01L27/24 ,  H01L21/321

Abstract: A memory device includes a metal structure, a first dielectric layer, a bottom electrode, a second dielectric layer, a resistance switching layer, and a top electrode. The first dielectric layer surrounds the metal structure. The bottom electrode is in contact with a top surface of the metal structure. The second dielectric layer surrounds the bottom electrode, in which a top surface of the bottom electrode is higher than a top surface of the second dielectric layer. The resistance switching layer is over the bottom electrode. The top electrode is over the resistance switching layer.

公开(公告)号：US11611038B2

公开(公告)日：2023-03-21

申请号：US17171278

申请日：2021-02-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-Chen Chang ,  Kuo-Chi Tu ,  Wen-Ting Chu ,  Chu-Jie Huang

IPC: H01L47/00 ,  H01L45/00 ,  H01L27/24

Abstract: Various embodiments of the present application are directed towards a resistive random-access memory (RRAM) cell comprising a barrier layer to constrain the movement of metal cations during operation of the RRAM cell. In some embodiments, the RRAM cell further comprises a bottom electrode, a top electrode, a switching layer, and an active metal layer. The switching layer, the barrier layer, and the active metal layer are stacked between the bottom and top electrodes, and the barrier layer is between the switching and active metal layers. The barrier layer is conductive and between has a lattice constant less than that of the active metal layer.

公开(公告)号：US10950784B2

公开(公告)日：2021-03-16

申请号：US16434414

申请日：2019-06-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Fu-Chen Chang ,  Kuo-Chi Tu ,  Wen-Ting Chu ,  Chu-Jie Huang

IPC: H01L29/04 ,  H01L45/00 ,  H01L27/24

Abstract: Various embodiments of the present application are directed towards a resistive random-access memory (RRAM) cell comprising a barrier layer to constrain the movement of metal cations during operation of the RRAM cell. In some embodiments, the RRAM cell further comprises a bottom electrode, a top electrode, a switching layer, and an active metal layer. The switching layer, the barrier layer, and the active metal layer are stacked between the bottom and top electrodes, and the barrier layer is between the switching and active metal layers. The barrier layer is conductive and has a lattice constant less than that of the active metal layer.