公开(公告)号：US11742290B2

公开(公告)日：2023-08-29

申请号：US17242783

申请日：2021-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Cheng Chin ,  Ming-Yuan Gao ,  Chen-Yi Niu ,  Yen-Chun Lin ,  Hsin-Ying Peng ,  Chih-Hsiang Chang ,  Pei-Hsuan Lee ,  Chi-Feng Lin ,  Chih-Chien Chi ,  Hung-Wen Su

IPC: H01L23/532 ,  H01L21/8234 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L27/088

CPC classification number: H01L23/53238 ,  H01L21/76846 ,  H01L21/76883 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/786 ,  H01L29/7851

Abstract: A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.

公开(公告)号：US20240373645A1

公开(公告)日：2024-11-07

申请号：US18777063

申请日：2024-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Yu Chen ,  Kuo-Chi Tu ,  Fu-Chen Chang ,  Chih-Hsiang Chang ,  Sheng-Hung Shih

IPC: H10B53/30 ,  G11C11/22 ,  H10B53/10

Abstract: In an embodiment, a structure includes one or more first transistors in a first region of a device, the one or more first transistors supporting a memory access function of the device. The structure includes one or more ferroelectric random access memory (FeRAM) capacitors in a first inter-metal dielectric (IMD) layer over the one or more first transistors in the first region. The structure also includes one or more metal-ferroelectric insulator-metal (MFM) decoupling capacitors in the first IMD layer in a second region of the device. The MFM capacitors may include two or more capacitors coupled in series to act as a voltage divider.

公开(公告)号：US11723294B2

公开(公告)日：2023-08-08

申请号：US16912341

申请日：2020-06-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsia-Wei Chen ,  Chih-Hung Pan ,  Chih-Hsiang Chang ,  Yu-Wen Liao ,  Wen-Ting Chu

IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

CPC classification number: H10N70/8416 ,  H10N70/023 ,  H10B63/30 ,  H10B63/80 ,  H10N70/063 ,  H10N70/24 ,  H10N70/826

Abstract: A method for fabricating a memory device is provided. The method includes forming a bottom electrode layer over a substrate; forming a buffer layer over the bottom electrode layer; performing a surface treatment to a top surface of the buffer layer; depositing a resistance switch layer over the top surface of the buffer layer after performing the surface treatment; forming a top electrode over the resistance switch layer; and patterning the resistance switch layer into a resistance switch element below the top electrode.

公开(公告)号：US20220293528A1

公开(公告)日：2022-09-15

申请号：US17242783

申请日：2021-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Cheng Chin ,  Ming-Yuan Gao ,  Chen-Yi Niu ,  Yen-Chun Lin ,  Hsin-Ying Peng ,  Chih-Hsiang Chang ,  Pei-Hsuan Lee ,  Chi-Feng Lin ,  Chih-Chien Chi ,  Hung-Wen Su

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L27/088 ,  H01L21/8234

Abstract: A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.

公开(公告)号：US20220231034A1

公开(公告)日：2022-07-21

申请号：US17712495

申请日：2022-04-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Yu Chen ,  Kuo-Chi Tu ,  Fu-Chen Chang ,  Chih-Hsiang Chang ,  Sheng-Hung Shih

IPC: H01L27/11507 ,  H01L27/11504 ,  G11C11/22 ,  H01L49/02

Abstract: In an embodiment, a structure includes one or more first transistors in a first region of a device, the one or more first transistors supporting a memory access function of the device. The structure includes one or more ferroelectric random access memory (FeRAM) capacitors in a first inter-metal dielectric (IMD) layer over the one or more first transistors in the first region. The structure also includes one or more metal-ferroelectric insulator-metal (MFM) decoupling capacitors in the first IMD layer in a second region of the device. The MFM capacitors may include two or more capacitors coupled in series to act as a voltage divider.

公开(公告)号：US20210035992A1

公开(公告)日：2021-02-04

申请号：US16663952

申请日：2019-10-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Yu Chen ,  Kuo-Chi Tu ,  Sheng-Hung Shih ,  Wen-Ting Chu ,  Chih-Hsiang Chang ,  Fu-Chen Chang

IPC: H01L27/11502

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a plurality of lower interconnect layers disposed within a lower dielectric structure over a substrate. A lower insulating structure is over the lower dielectric structure and has sidewalls extending through the lower insulating structure. A bottom electrode is arranged along the sidewalls and an upper surface of the lower insulating structure. The upper surface of the lower insulating structure extends past outermost sidewalls of the bottom electrode. A data storage structure is disposed on the bottom electrode and is configured to store a data state. A top electrode is disposed on the data storage structure. The bottom electrode has interior sidewalls coupled to a horizontally extending surface to define a recess within an upper surface of the bottom electrode. The horizontally extending surface is below the upper surface of the lower insulating structure.

公开(公告)号：US20240413087A1

公开(公告)日：2024-12-12

申请号：US18790012

申请日：2024-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Cheng Chin ,  Ming-Yuan Gao ,  Chen-Yi Niu ,  Yen-Chun Lin ,  Hsin-Ying Peng ,  Chih-Hsiang Chang ,  Pei-Hsuan Lee ,  Chi-Feng Lin ,  Chih-Chien Chi ,  Hung-Wen Su

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.

公开(公告)号：US12165975B2

公开(公告)日：2024-12-10

申请号：US18351957

申请日：2023-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Cheng Chin ,  Ming-Yuan Gao ,  Chen-Yi Niu ,  Yen-Chun Lin ,  Hsin-Ying Peng ,  Chih-Hsiang Chang ,  Pei-Hsuan Lee ,  Chi-Feng Lin ,  Chih-Chien Chi ,  Hung-Wen Su

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.

公开(公告)号：US11227872B2

公开(公告)日：2022-01-18

申请号：US16394207

申请日：2019-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hsiang Chang ,  Kuo-Chi Tu ,  Sheng-Hung Shih ,  Wen-Ting Chu ,  Tzu-Yu Chen ,  Fu-Chen Chang

IPC: H01L27/11585 ,  G11C11/22 ,  H01L29/78 ,  H01L29/51 ,  H01L29/66 ,  H01L21/28

Abstract: In some embodiments, the present disclosure relates to an integrated chip including one or more lower interconnect layers arranged within one or more stacked inter-layer dielectric layers over a substrate. A bottom electrode is disposed over the one or more interconnect layers, and a top electrode is disposed over the bottom electrode. A ferroelectric layer is disposed between and contacts a first surface of the bottom electrode and a second surface of the top electrode. The ferroelectric layer includes a protrusion that extends past outer surfaces of the top electrode and the bottom electrode along a first direction that is perpendicular to a second direction that is normal to the first surface. The protrusion is confined between lines that extend along the first and second surface.

公开(公告)号：US11183503B2

公开(公告)日：2021-11-23

申请号：US16663952

申请日：2019-10-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Yu Chen ,  Kuo-Chi Tu ,  Sheng-Hung Shih ,  Wen-Ting Chu ,  Chih-Hsiang Chang ,  Fu-Chen Chang

IPC: H01L27/11502 ,  H01L27/11507 ,  H01L49/02 ,  G11C11/22 ,  H01L27/11504

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a plurality of lower interconnect layers disposed within a lower dielectric structure over a substrate. A lower insulating structure is over the lower dielectric structure and has sidewalls extending through the lower insulating structure. A bottom electrode is arranged along the sidewalls and an upper surface of the lower insulating structure. The upper surface of the lower insulating structure extends past outermost sidewalls of the bottom electrode. A data storage structure is disposed on the bottom electrode and is configured to store a data state. A top electrode is disposed on the data storage structure. The bottom electrode has interior sidewalls coupled to a horizontally extending surface to define a recess within an upper surface of the bottom electrode. The horizontally extending surface is below the upper surface of the lower insulating structure.