公开(公告)号：US20240371726A1

公开(公告)日：2024-11-07

申请号：US18778763

申请日：2024-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Rong Chun ,  Kuo-Lung Pan ,  Pei-Hsuan Lee ,  Chien Ling Hwang ,  Yu-Chia Lai ,  Tin-Hao Kuo ,  Hao-Yi Tsai ,  Chen-Hua Yu

IPC: H01L23/40 ,  H01L23/00

Abstract: In an embodiment, a device includes: a package component including integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure over the encapsulant and the integrated circuit dies, and sockets over the redistribution structure; a mechanical brace physically coupled to the sockets, the mechanical brace having openings, each one of the openings exposing a respective one of the sockets; a thermal module physically and thermally coupled to the encapsulant and the integrated circuit dies; and bolts extending through the thermal module, the mechanical brace, and the package component.

公开(公告)号：US11380542B2

公开(公告)日：2022-07-05

申请号：US17013316

申请日：2020-09-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chien Chi ,  Pei-Hsuan Lee ,  Hung-Wen Su ,  Hsiao-Kuan Wei ,  Jui-Fen Chien ,  Hsin-Yun Hsu

IPC: H01L21/02 ,  H01L21/20 ,  H01L29/66 ,  H01L21/762 ,  H01L29/49 ,  H01L21/324 ,  H01L21/28 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78 ,  H01L21/3205 ,  H01L29/417 ,  H01L21/3105 ,  H01L21/768

Abstract: Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.

公开(公告)号：US10727118B2

公开(公告)日：2020-07-28

申请号：US15964430

申请日：2018-04-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jung-Tang Wu ,  Pao-Sheng Chen ,  Pei-Hsuan Lee ,  Szu-Hua Wu ,  Chih-Chien Chi

IPC: H01L21/768 ,  H01L21/67 ,  H01L21/02

Abstract: In a method for manufacturing a semiconductor device, a substrate is provided. Various first metal layers are formed on the substrate. A dielectric structure with through holes is formed over the first metal layers. The through holes expose the first metal layers. A pre-clean operation is performed on the dielectric structure and the first metal layers by using an alcohol base vapor and/or an aldehyde base vapor as a reduction agent. Conductors are formed on the first metal layers. In forming the conductors, the through holes are filled with the conductors.

公开(公告)号：US10510623B2

公开(公告)日：2019-12-17

申请号：US15855080

申请日：2017-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Wei Fang ,  Jing-Sen Wang ,  Yuan-Yao Chang ,  Wei-Ray Lin ,  Ting-Hua Hsieh ,  Pei-Hsuan Lee ,  Yu-Hsuan Huang

IPC: H01L21/66 ,  G03F7/20 ,  G06F17/50 ,  H01L21/768 ,  G01N21/88 ,  H01L21/76 ,  G01N21/95 ,  G01N21/93 ,  G06T7/00 ,  H01L21/8234

Abstract: A method for inline inspection during semiconductor wafer fabrication is provided. The method includes forming a plurality of test structures on a semiconductor wafer along two opposite directions. An offset distance between a sample feature and a target feature of each of the test structures increases gradually along the two opposite directions. The method further includes producing an image of the test structures. The method also includes performing image analysis of the image to recognize a position with an extreme of a gray level. In addition, the method includes calculating an overlay error according to the recognized position.

公开(公告)号：US09887073B2

公开(公告)日：2018-02-06

申请号：US14622397

申请日：2015-02-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Chien Chi ,  Hung-Wen Su ,  Pei-Hsuan Lee

IPC: H01J37/34 ,  C23C14/35 ,  C23C14/04

CPC classification number: H01J37/3447 ,  C23C14/046 ,  C23C14/35 ,  H01J37/3402

Abstract: A physical vapor deposition system includes a chamber, a cover plate, a pedestal, and a collimator. The cover plate is disposed on the chamber for holding a target. The pedestal is disposed in the chamber for supporting a wafer. The collimator is mounted between the cover plate and the pedestal. The collimator includes a plurality of sidewall sheets together forming a plurality of passages. At least one of the passages has an entrance and an exit opposite to the entrance. The entrance faces the cover plate, and the exit faces the pedestal. A thickness of one of the sidewall sheets at the entrance is thinner than a thickness of the sidewall sheet at the exit.

公开(公告)号：US11742290B2

公开(公告)日：2023-08-29

申请号：US17242783

申请日：2021-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Cheng Chin ,  Ming-Yuan Gao ,  Chen-Yi Niu ,  Yen-Chun Lin ,  Hsin-Ying Peng ,  Chih-Hsiang Chang ,  Pei-Hsuan Lee ,  Chi-Feng Lin ,  Chih-Chien Chi ,  Hung-Wen Su

IPC: H01L23/532 ,  H01L21/8234 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L27/088

CPC classification number: H01L23/53238 ,  H01L21/76846 ,  H01L21/76883 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/786 ,  H01L29/7851

Abstract: A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.

公开(公告)号：US20200335477A1

公开(公告)日：2020-10-22

申请号：US16923115

申请日：2020-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Albert Wan ,  Ching-Hua Hsieh ,  Chung-Hao Tsai ,  Chuei-Tang Wang ,  Chao-Wen Shih ,  Han-Ping Pu ,  Chien-Ling Hwang ,  Pei-Hsuan Lee ,  Tzu-Chun Tang ,  Yu-Ting Chiu ,  Jui-Chang Kuo

IPC: H01L23/00 ,  H01L23/538 ,  H01L21/768 ,  H01L21/48 ,  H01L23/66 ,  H01L25/00 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31 ,  H01L21/683

Abstract: A method of manufacturing an integrated fan-out (InFO) package includes at least the following steps. A package array is formed. A core layer and a dielectric layer are sequentially stacked over the package array. The core layer includes a plurality of cavities. A plurality of first conductive patches is formed on the dielectric layer above the cavities.

公开(公告)号：US10756052B2

公开(公告)日：2020-08-25

申请号：US16524146

申请日：2019-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Albert Wan ,  Ching-Hua Hsieh ,  Chung-Hao Tsai ,  Chuei-Tang Wang ,  Chao-Wen Shih ,  Han-Ping Pu ,  Chien-Ling Hwang ,  Pei-Hsuan Lee ,  Tzu-Chun Tang ,  Yu-Ting Chiu ,  Jui-Chang Kuo

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/538 ,  H01L21/768 ,  H01L21/48 ,  H01L23/66 ,  H01L25/00 ,  H01L25/065 ,  H01L23/31 ,  H01L21/683 ,  H01L23/544

Abstract: A method of manufacturing an integrated fan-out (InFO) package includes at least the following steps. A package array is formed. A dielectric layer having a core layer formed thereon is provided. The core layer includes a plurality of cavities penetrating through the core layer. The dielectric layer and the core layer are attached onto the package array such that the core layer is located between the dielectric layer and the package array. A plurality of first conductive patches is formed on the dielectric layer above the cavities.

公开(公告)号：US10366966B1

公开(公告)日：2019-07-30

申请号：US15981929

申请日：2018-05-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Albert Wan ,  Ching-Hua Hsieh ,  Chung-Hao Tsai ,  Chuei-Tang Wang ,  Chao-Wen Shih ,  Han-Ping Pu ,  Chien-Ling Hwang ,  Pei-Hsuan Lee ,  Tzu-Chun Tang ,  Yu-Ting Chiu ,  Jui-Chang Kuo

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/538 ,  H01L21/768 ,  H01L21/48 ,  H01L23/66 ,  H01L25/00 ,  H01L25/065 ,  H01L23/31

Abstract: A method of manufacturing an integrated fan-out (InFO) package includes at least the following steps. A package array is formed. A dielectric layer and a core material layer are sequentially formed on a first carrier. A portion of the core material layer is removed to form a core layer having a plurality of cavities. The first carrier, the dielectric layer, and the core layer are attached onto the package array such that the core layer is located between the dielectric layer and the package array. The first carrier is removed from the dielectric layer. A plurality of first conductive patches is formed on the dielectric layer above the cavities.

公开(公告)号：US12159830B2

公开(公告)日：2024-12-03

申请号：US18068615

申请日：2022-12-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hui Lee ,  Po-Hsiang Huang ,  Wen-Sheh Huang ,  Jen Hung Wang ,  Su-Jen Sung ,  Chih-Chien Chi ,  Pei-Hsuan Lee

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: Interconnect structures exhibiting reduced accumulation of copper vacancies along interfaces between contact etch stop layers (CESLs) and interconnects, along with methods for fabrication, are disclosed herein. A method includes forming a copper interconnect in a dielectric layer and depositing a metal nitride CESL over the copper interconnect and the dielectric layer. An interface between the metal nitride CESL and the copper interconnect has a first surface nitrogen concentration, a first nitrogen concentration and/or a first number of nitrogen-nitrogen bonds. A nitrogen plasma treatment is performed to modify the interface between the metal nitride CESL and the copper interconnect. The nitrogen plasma treatment increases the first surface nitrogen concentration to a second surface nitrogen concentration, the first nitrogen concentration to a second nitrogen concentration, and/or the first number of nitrogen-nitrogen bonds to a second number of nitrogen-nitrogen bonds, each of which minimizes accumulation of copper vacancies at the interface.