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    MAGNETIC MEMORY DEVICE
    1.
    发明申请
    MAGNETIC MEMORY DEVICE 有权

    公开(公告)号：US20220328083A1

    公开(公告)日：2022-10-13

    申请号：US17537937

    申请日：2021-11-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seung Pil KO ,  Yongjae KIM ,  Geonhee BAE ,  Gawon LEE ,  Kilho LEE

    IPC: G11C11/16 ,  H01L23/528 ,  H01L43/10 ,  H01L43/08 ,  H01L27/22 ,  H01L43/02

    Abstract: A magnetic memory device may include a substrate including a first region and a second region, a first interlayer insulating layer on the substrate, a first capping layer on the first interlayer insulating layer, the first capping layer covering the first and second regions of the substrate, a second interlayer insulating layer on a portion of the first capping layer covering the first region of the substrate, a bottom electrode contact included in the second interlayer insulating layer, a magnetic tunnel junction pattern on the bottom electrode contact, and a second capping layer on the second interlayer insulating layer, the second capping layer being in contact with the first capping layer on the second region of the substrate.

    NONVOLATILE MEMORY DEVICE
    2.
    发明申请
    NONVOLATILE MEMORY DEVICE 有权

    公开(公告)号：US20240389470A1

    公开(公告)日：2024-11-21

    申请号：US18531200

    申请日：2023-12-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kilho LEE ,  Dahye SHIN

    IPC: H10N50/80 ,  G11C11/16 ,  H10B61/00 ,  H10N50/10

    Abstract: Provided is a nonvolatile memory device equipped with an information storage device with improved reliability. The nonvolatile memory device includes a substrate in which a cell area and a peripheral area are defined, a multi-wire layer disposed on the cell area and the peripheral area and including metal wires of a multilayer, and an information storing layer including a plurality of information storage devices arranged on the multi-wire layer of the cell area in a two-dimensional array structure, in which a first metal wire arranged in an uppermost portion of the multi-wire layer of the peripheral area is located at a level lower than a level of a second metal wire arranged in an uppermost portion of the multi-wire layer of the cell area.

    MAGNETIC MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME
    3.
    发明申请
    MAGNETIC MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20200020847A1

    公开(公告)日：2020-01-16

    申请号：US16286718

    申请日：2019-02-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kilho LEE ,  Gwanhyeob KOH ,  Yongjae KIM ,  Yoonjong SONG

    IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

    Abstract: A magnetic memory device including a substrate including a cell region and a peripheral circuit region; a first interlayer insulating layer covering the cell region and the peripheral circuit region of the substrate; interconnection lines in the first interlayer insulating layer; a peripheral conductive line and a peripheral conductive contact on the first interlayer insulating layer on the peripheral circuit region, the peripheral conductive contact being between the peripheral conductive line and a corresponding one of the interconnection lines; a bottom electrode contact on the first interlayer insulating layer on the cell region and connected to a corresponding one of the interconnection lines; and a data storage pattern on the bottom electrode contact, wherein the peripheral conductive line is at a height between a top surface of the bottom electrode contact and a bottom surface of the bottom electrode contact.

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    4.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20250063739A1

    公开(公告)日：2025-02-20

    申请号：US18425147

    申请日：2024-01-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kilho LEE ,  Daeshik KIM

    IPC: H10B61/00

    Abstract: A semiconductor device may include a substrate, data storage patterns on the substrate and spaced apart from each other in a first direction and a second direction that intersect each other and are parallel to a top surface of the substrate, first cell conductive lines that extend in the first direction and are spaced apart from each other in the second direction on the data storage patterns, cell via contacts that are spaced apart from each other in the first direction and disposed between a pair of the first cell conductive lines, dummy data storage patterns that are spaced apart from each other in the first direction between the first cell conductive lines and are disposed between the cell via contacts, and upper conductive lines on the cell via contacts and electrically connected to the cell via contacts, respectively.

    SEMICONDUCTOR DEVICE
    5.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240114700A1

    公开(公告)日：2024-04-04

    申请号：US18448615

    申请日：2023-08-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yongjae LEE ,  Seung Pil KO ,  Kilho LEE ,  Jeongjin LEE

    IPC: H10B61/00 ,  H01L23/00 ,  H01L27/146 ,  H10B80/00

    CPC classification number: H10B61/22 ,  H01L24/08 ,  H01L27/14634 ,  H10B80/00 ,  H01L2224/08145

    Abstract: A semiconductor device includes cell lower conductive lines and peripheral lower conductive lines on a substrate, lower electrode contacts on the cell lower conductive lines, peripheral conductive contacts on the peripheral lower conductive lines, variable resistance patterns horizontally spaced apart from each other on the lower electrode contacts. The lower electrode contacts are respectively connected to the variable resistance patterns. Peripheral conductive lines are horizontally spaced apart from the variable resistance patterns on the peripheral conductive contacts. The peripheral conductive contacts are connected to the peripheral conductive lines. The cell and peripheral lower conductive lines are connected to the lower electrode contacts and the peripheral conductive contacts, respectively. The cell and peripheral lower conductive lines are at the same height. A pitch of the cell lower conductive lines directly adjacent to each other is greater than a pitch of the peripheral lower conductive lines directly adjacent to each other.

    METHOD OF FABRICATING MEMORY DEVICE
    7.
    发明公开
    METHOD OF FABRICATING MEMORY DEVICE 审中-公开

    公开(公告)号：US20230217835A1

    公开(公告)日：2023-07-06

    申请号：US18145228

    申请日：2022-12-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Manjin EOM ,  Gawon LEE ,  Seungpil KO ,  Kilho LEE

    IPC: H10N50/01 ,  H01J37/305 ,  H10B61/00 ,  H10N50/80

    CPC classification number: H01L43/12 ,  H01J37/305 ,  H01L27/222 ,  H01L43/02

    Abstract: A method of manufacturing a memory device includes sequentially forming a first magnetization layer, a tunnel barrier layer, and a second magnetization layer on each other; forming a magnetic tunnel junction structure by patterning the first magnetization layer, the tunnel barrier layer, and the second magnetization layer; forming a sidewall metal layer by etching a portion of a redeposited metal covering a sidewall of the magnetic tunnel junction structure; performing an oxidizing operation that includes oxidizing an exposed surface of the sidewall metal layer to provide an oxidized sidewall metal layer; and performing an irradiating operation that includes irradiating an ion beam towards the oxidized sidewall metal layer. A sidewall insulating layer covering a sidewall of the magnetic tunnel junction structure is formed by alternately performing the oxidizing operation and the irradiating operation two or more times.

    SEMICONDUCTOR DEVICE
    9.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20190267046A1

    公开(公告)日：2019-08-29

    申请号：US16411106

    申请日：2019-05-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kilho LEE ,  Gwanhyeob KOH ,  Junhee LIM ,  Hongsoo KIM ,  Chang-hoon JEON

    IPC: G11C5/06 ,  H01L27/11573 ,  H01L27/22 ,  H01L27/1157 ,  H01L43/10 ,  G11C13/00 ,  H01L25/18 ,  G11C11/16 ,  G11C16/04

    Abstract: A first memory section is disposed on a substrate. A second memory section is vertically stacked on the first memory section. The first memory section is provided between the substrate and the second memory section. The first memory section includes a flash memory cell structure, and the second memory section includes a variable resistance memory cell structure. The flash memory cell structure includes at least one cell string comprising a plurality of first memory cells connected in series to each other and a bit line on the substrate connected to the at least one cell string. The bit line is interposed vertically between the at least one cell string and the second memory section and connected to the second memory section.

    MEMORY DEVICES AND METHODS OF FABRICATING THE SAME
    10.
    发明申请
    MEMORY DEVICES AND METHODS OF FABRICATING THE SAME 审中-公开
    记忆装置及其制造方法

    公开(公告)号：US20150017743A1

    公开(公告)日：2015-01-15

    申请号：US14498465

    申请日：2014-09-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Kilho LEE ,  Ki Joon KIM ,  Se Woong PARK

    IPC: H01L43/12 ,  H01L27/22

    CPC classification number: H01L43/12 ,  H01L27/10888 ,  H01L27/222 ,  H01L27/228 ,  H01L29/82

    Abstract: Memory devices and methods of fabricating the same include a substrate including a cell region and a peripheral circuit region, data storages on the cell region, first bit lines on and coupled to the data storages, first contacts coupled to peripheral transistors on the peripheral circuit region, and second bit lines on and coupled to the first contacts. The second bit lines may each have a lowermost surface lower than a lowermost surface of the data storages.

    Abstract translation: 存储器件及其制造方法包括：包括单元区域和外围电路区域的衬底，在单元区域上的数据存储，在数据存储器上并耦合到数据存储器的第一位线，耦合到外围电路区域上的外围晶体管的第一触点 以及在第一触点上并耦合到第一触点的第二位线。 第二位线可以各自具有低于数据存储器的最低表面的最下表面。

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